Pica: Add command list registers.
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@ -7,11 +7,11 @@
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#include "core/core.h"
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#include "core/mem_map.h"
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#include "core/hle/kernel/thread.h"
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#include "core/hw/lcd.h"
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#include "video_core/video_core.h"
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#include "core/hle/kernel/thread.h"
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namespace LCD {
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@ -89,31 +89,70 @@ inline void Read(T &var, const u32 addr) {
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case REG_FRAMEBUFFER_TOP_LEFT_1:
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var = g_regs.framebuffer_top_left_1;
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break;
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case REG_FRAMEBUFFER_TOP_LEFT_2:
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var = g_regs.framebuffer_top_left_2;
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break;
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case REG_FRAMEBUFFER_TOP_RIGHT_1:
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var = g_regs.framebuffer_top_right_1;
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break;
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case REG_FRAMEBUFFER_TOP_RIGHT_2:
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var = g_regs.framebuffer_top_right_2;
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break;
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case REG_FRAMEBUFFER_SUB_LEFT_1:
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var = g_regs.framebuffer_sub_left_1;
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break;
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case REG_FRAMEBUFFER_SUB_RIGHT_1:
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var = g_regs.framebuffer_sub_right_1;
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break;
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case CommandListSize:
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var = g_regs.command_list_size;
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break;
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case CommandListAddress:
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var = g_regs.command_list_address;
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break;
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case ProcessCommandList:
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var = g_regs.command_processing_enabled;
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break;
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default:
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ERROR_LOG(LCD, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
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break;
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}
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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ERROR_LOG(LCD, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
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switch (addr) {
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case CommandListSize:
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g_regs.command_list_size = data;
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break;
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case CommandListAddress:
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g_regs.command_list_address = data;
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break;
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case ProcessCommandList:
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g_regs.command_processing_enabled = data;
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if (g_regs.command_processing_enabled & 1)
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{
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// u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3);
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ERROR_LOG(LCD, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3);
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// TODO: Process command list!
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}
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break;
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default:
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ERROR_LOG(LCD, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
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break;
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}
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}
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// Explicitly instantiate template functions because we aren't defining this in the header:
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@ -17,6 +17,10 @@ struct Registers {
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u32 framebuffer_sub_left_2;
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u32 framebuffer_sub_right_1;
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u32 framebuffer_sub_right_2;
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u32 command_list_size;
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u32 command_list_address;
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u32 command_processing_enabled;
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};
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extern Registers g_regs;
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@ -57,12 +61,16 @@ enum {
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REG_FRAMEBUFFER_SUB_LEFT_2 = 0x1EF0056C, // Sub LCD, second framebuffer
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REG_FRAMEBUFFER_SUB_RIGHT_1 = 0x1EF00594, // Sub LCD, unused first framebuffer
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REG_FRAMEBUFFER_SUB_RIGHT_2 = 0x1EF00598, // Sub LCD, unused second framebuffer
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CommandListSize = 0x1EF018E0,
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CommandListAddress = 0x1EF018E8,
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ProcessCommandList = 0x1EF018F0,
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};
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/// Framebuffer location
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enum FramebufferLocation {
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FRAMEBUFFER_LOCATION_UNKNOWN, ///< Framebuffer location is unknown
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FRAMEBUFFER_LOCATION_FCRAM, ///< Framebuffer is in the GSP heap
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FRAMEBUFFER_LOCATION_FCRAM, ///< Framebuffer is in the GSP heap
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FRAMEBUFFER_LOCATION_VRAM, ///< Framebuffer is in VRAM
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};
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