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arm: Clean out armos.h and armmmu.h

This commit is contained in:
Lioncash 2015-01-30 15:48:57 -05:00
parent 88a62b671b
commit 904194c3e8
2 changed files with 23 additions and 181 deletions
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99
src/core/arm/skyeye_common/armmmu.h
View File

@ -18,19 +18,10 @@
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#ifndef _ARMMMU_H_ #pragma once
#define _ARMMMU_H_
// Register numbers in the MMU
#define WORD_SHT 2 enum
#define WORD_SIZE (1<<WORD_SHT)
/* The MMU is accessible with MCR and MRC operations to copro 15: */
#define MMU_COPRO (15)
/* Register numbers in the MMU: */
typedef enum mmu_regnum_t
{ {
MMU_ID = 0, MMU_ID = 0,
MMU_CONTROL = 1, MMU_CONTROL = 1,
@ -44,94 +35,22 @@ typedef enum mmu_regnum_t
MMU_TLB_LOCKDOWN = 10, MMU_TLB_LOCKDOWN = 10,
MMU_PID = 13, MMU_PID = 13,
/*MMU_V4 */ // MMU_V4
MMU_V4_CACHE_OPS = 7, MMU_V4_CACHE_OPS = 7,
MMU_V4_TLB_OPS = 8, MMU_V4_TLB_OPS = 8,
/*MMU_V3 */ // MMU_V3
MMU_V3_FLUSH_TLB = 5, MMU_V3_FLUSH_TLB = 5,
MMU_V3_FLUSH_TLB_ENTRY = 6, MMU_V3_FLUSH_TLB_ENTRY = 6,
MMU_V3_FLUSH_CACHE = 7, MMU_V3_FLUSH_CACHE = 7,
/*MMU Intel SA-1100 */ // MMU Intel SA-1100
MMU_SA_RB_OPS = 9, MMU_SA_RB_OPS = 9,
MMU_SA_DEBUG = 14, MMU_SA_DEBUG = 14,
MMU_SA_CP15_R15 = 15, MMU_SA_CP15_R15 = 15,
//chy 2003-08-24
/*Intel xscale CP15 */ // Intel xscale CP15
XSCALE_CP15_CACHE_TYPE = 0, XSCALE_CP15_CACHE_TYPE = 0,
XSCALE_CP15_AUX_CONTROL = 1, XSCALE_CP15_AUX_CONTROL = 1,
XSCALE_CP15_COPRO_ACCESS = 15, XSCALE_CP15_COPRO_ACCESS = 15,
};
} mmu_regnum_t;
/* Bits in the control register */
#define CONTROL_MMU (1<<0)
#define CONTROL_ALIGN_FAULT (1<<1)
#define CONTROL_CACHE (1<<2)
#define CONTROL_DATA_CACHE (1<<2)
#define CONTROL_WRITE_BUFFER (1<<3)
#define CONTROL_BIG_ENDIAN (1<<7)
#define CONTROL_SYSTEM (1<<8)
#define CONTROL_ROM (1<<9)
#define CONTROL_UNDEFINED (1<<10)
#define CONTROL_BRANCH_PREDICT (1<<11)
#define CONTROL_INSTRUCTION_CACHE (1<<12)
#define CONTROL_VECTOR (1<<13)
#define CONTROL_RR (1<<14)
#define CONTROL_L4 (1<<15)
#define CONTROL_XP (1<<23)
#define CONTROL_EE (1<<25)
/*Macro defines for MMU state*/
#define MMU_CTL (state->mmu.control)
#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
#define MMU_Disabled (!(MMU_Enabled))
#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
#define MMU_CacheDisabled (!(MMU_CacheEnabled))
#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
#define MMU_WBDisabled (!(MMU_WBEnabled))
/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
#define PID_VA_MAP_MASK 0xfe000000
//#define mmu_pid_va_map(va) ({\
// ARMword ret; \
// if ((va) & PID_VA_MAP_MASK)\
// ret = (va); \
// else \
// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
// ret;\
//})
#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
/* FS[3:0] in the fault status register: */
typedef enum fault_t
{
NO_FAULT = 0x0,
ALIGNMENT_FAULT = 0x1,
SECTION_TRANSLATION_FAULT = 0x5,
PAGE_TRANSLATION_FAULT = 0x7,
SECTION_DOMAIN_FAULT = 0x9,
PAGE_DOMAIN_FAULT = 0xB,
SECTION_PERMISSION_FAULT = 0xD,
SUBPAGE_PERMISSION_FAULT = 0xF,
/* defined by skyeye */
TLB_READ_MISS = 0x30,
TLB_WRITE_MISS = 0x40,
} fault_t;
#endif /* _ARMMMU_H_ */

87
src/core/arm/skyeye_common/armos.h
View File

@ -13,26 +13,12 @@
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <stdint.h> //
// SWI Numbers
#if FAST_MEMORY //
/* in user mode, mmap_base will be on initial brk,
set at the first mmap request */
#define mmap_base -1
#else
#define mmap_base 0x50000000
#endif
static long mmap_next_base = mmap_base;
//static mmap_area_t* new_mmap_area(int sim_addr, int len);
static char mmap_mem_write(short size, int addr, uint32_t value);
static char mmap_mem_read(short size, int addr, uint32_t * value);
/***************************************************************************\
* SWI numbers *
\***************************************************************************/
#define SWI_Syscall 0x0 #define SWI_Syscall 0x0
#define SWI_Exit 0x1 #define SWI_Exit 0x1
@ -58,15 +44,6 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
#define SWI_ExitGroup 0xf8 #define SWI_ExitGroup 0xf8
#if 0
#define SWI_Time 0xd
#define SWI_Clock 0x61
#define SWI_Time 0x63
#define SWI_Remove 0x64
#define SWI_Rename 0x65
#define SWI_Flen 0x6c
#endif
#define SWI_Uname 0x7a #define SWI_Uname 0x7a
#define SWI_Fcntl 0xdd #define SWI_Fcntl 0xdd
#define SWI_Fstat64 0xc5 #define SWI_Fstat64 0xc5
@ -75,57 +52,3 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */ #define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
/***************************************************************************\
* SWI structures *
\***************************************************************************/
/* Arm binaries (for now) only support 32 bit, and expect to receive
32-bit compliant structure in return of a systen call. Because
we use host system calls to emulate system calls, the returned
structure can be 32-bit compliant or 64-bit compliant, depending
on the OS running skyeye. Therefore, we need a fixed size structure
adapted to arm.*/
/* Borrowed from qemu */
struct target_stat64 {
unsigned short st_dev;
unsigned char __pad0[10];
uint32_t __st_ino;
unsigned int st_mode;
unsigned int st_nlink;
uint32_t st_uid;
uint32_t st_gid;
unsigned short st_rdev;
unsigned char __pad3[10];
unsigned char __pad31[4];
long long st_size;
uint32_t st_blksize;
unsigned char __pad32[4];
uint32_t st_blocks;
uint32_t __pad4;
uint32_t st32_atime;
uint32_t __pad5;
uint32_t st32_mtime;
uint32_t __pad6;
uint32_t st32_ctime;
uint32_t __pad7;
unsigned long long st_ino;
};// __attribute__((packed));
struct target_tms32 {
uint32_t tms_utime;
uint32_t tms_stime;
uint32_t tms_cutime;
uint32_t tms_cstime;
};
struct target_timeval32 {
uint32_t tv_sec; /* seconds */
uint32_t tv_usec; /* microseconds */
};
struct target_timezone32 {
int32_t tz_minuteswest; /* minutes west of Greenwich */
int32_t tz_dsttime; /* type of DST correction */
};