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dyncom: const correctness changes

This commit is contained in:
Lioncash 2015-12-06 15:03:06 -05:00
parent 87df493b5b
commit d03e7f08ff
3 changed files with 7 additions and 7 deletions
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2
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -51,7 +51,7 @@ enum {
typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
static bool CondPassed(ARMul_State* cpu, unsigned int cond) { static bool CondPassed(const ARMul_State* cpu, unsigned int cond) {
const bool n_flag = cpu->NFlag != 0; const bool n_flag = cpu->NFlag != 0;
const bool z_flag = cpu->ZFlag != 0; const bool z_flag = cpu->ZFlag != 0;
const bool c_flag = cpu->CFlag != 0; const bool c_flag = cpu->CFlag != 0;

4
src/core/arm/dyncom/arm_dyncom_run.h
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@ -30,7 +30,7 @@
* @return If the PC is being read, then the word-aligned PC value is returned. * @return If the PC is being read, then the word-aligned PC value is returned.
* If the PC is not being read, then the value stored in the register is returned. * If the PC is not being read, then the value stored in the register is returned.
*/ */
static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) { static inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn]; return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
} }
@ -43,6 +43,6 @@ static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
* @return If the PC is being read, then the incremented PC value is returned. * @return If the PC is being read, then the incremented PC value is returned.
* If the PC is not being read, then the values stored in the register is returned. * If the PC is not being read, then the values stored in the register is returned.
*/ */
static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) { static inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) {
return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn]; return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
} }

8
src/core/arm/skyeye_common/vfp/vfp_helper.h
View File

@ -249,7 +249,7 @@ enum : u32 {
VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL) VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
}; };
static inline int vfp_single_type(vfp_single* s) static inline int vfp_single_type(const vfp_single* s)
{ {
int type = VFP_NUMBER; int type = VFP_NUMBER;
if (s->exponent == 255) { if (s->exponent == 255) {
@ -293,7 +293,7 @@ static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
// Re-pack a single-precision float. This assumes that the float is // Re-pack a single-precision float. This assumes that the float is
// already normalised such that the MSB is bit 30, _not_ bit 31. // already normalised such that the MSB is bit 30, _not_ bit 31.
static inline s32 vfp_single_pack(vfp_single* s) static inline s32 vfp_single_pack(const vfp_single* s)
{ {
u32 val = (s->sign << 16) + u32 val = (s->sign << 16) +
(s->exponent << VFP_SINGLE_MANTISSA_BITS) + (s->exponent << VFP_SINGLE_MANTISSA_BITS) +
@ -335,7 +335,7 @@ struct vfp_double {
#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1)) #define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1)) #define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
static inline int vfp_double_type(vfp_double* s) static inline int vfp_double_type(const vfp_double* s)
{ {
int type = VFP_NUMBER; int type = VFP_NUMBER;
if (s->exponent == 2047) { if (s->exponent == 2047) {
@ -379,7 +379,7 @@ static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
// Re-pack a double-precision float. This assumes that the float is // Re-pack a double-precision float. This assumes that the float is
// already normalised such that the MSB is bit 30, _not_ bit 31. // already normalised such that the MSB is bit 30, _not_ bit 31.
static inline s64 vfp_double_pack(vfp_double* s) static inline s64 vfp_double_pack(const vfp_double* s)
{ {
u64 val = ((u64)s->sign << 48) + u64 val = ((u64)s->sign << 48) +
((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) + ((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +