100 lines
2.9 KiB
C++
100 lines
2.9 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <vector>
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#include <queue>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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enum class SubmissionMode : u32 {
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IncreasingOld = 0,
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Increasing = 1,
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NonIncreasingOld = 2,
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NonIncreasing = 3,
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Inline = 4,
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IncreaseOnce = 5
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};
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struct CommandListHeader {
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union {
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u64 raw;
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BitField<0, 40, GPUVAddr> addr;
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BitField<41, 1, u64> is_non_main;
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BitField<42, 21, u64> size;
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};
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};
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static_assert(sizeof(CommandListHeader) == sizeof(u64), "CommandListHeader is incorrect size");
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union CommandHeader {
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u32 argument;
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BitField<0, 13, u32> method;
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BitField<0, 24, u32> method_count_;
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BitField<13, 3, u32> subchannel;
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BitField<16, 13, u32> arg_count;
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BitField<16, 13, u32> method_count;
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BitField<29, 3, SubmissionMode> mode;
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};
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static_assert(std::is_standard_layout_v<CommandHeader>, "CommandHeader is not standard layout");
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static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
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class GPU;
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using CommandList = std::vector<Tegra::CommandListHeader>;
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/**
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* The DmaPusher class implements DMA submission to FIFOs, providing an area of memory that the
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* emulated app fills with commands and tells PFIFO to process. The pushbuffers are then assembled
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* into a "command stream" consisting of 32-bit words that make up "commands".
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* See https://envytools.readthedocs.io/en/latest/hw/fifo/dma-pusher.html#fifo-dma-pusher for
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* details on this implementation.
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*/
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class DmaPusher {
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public:
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explicit DmaPusher(GPU& gpu);
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~DmaPusher();
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void Push(CommandList&& entries) {
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dma_pushbuffer.push(std::move(entries));
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}
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void DispatchCalls();
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private:
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bool Step();
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void SetState(const CommandHeader& command_header);
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void CallMethod(u32 argument) const;
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GPU& gpu;
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std::queue<CommandList> dma_pushbuffer; ///< Queue of command lists to be processed
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std::size_t dma_pushbuffer_subindex{}; ///< Index within a command list within the pushbuffer
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struct DmaState {
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u32 method; ///< Current method
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u32 subchannel; ///< Current subchannel
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u32 method_count; ///< Current method count
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u32 length_pending; ///< Large NI command length pending
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bool non_incrementing; ///< Current command<6E>s NI flag
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};
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DmaState dma_state{};
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bool dma_increment_once{};
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GPUVAddr dma_put{}; ///< pushbuffer current end address
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GPUVAddr dma_get{}; ///< pushbuffer current read address
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GPUVAddr dma_mget{}; ///< main pushbuffer last read address
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bool ib_enable{true}; ///< IB mode enabled
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bool non_main{}; ///< non-main pushbuffer active
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};
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} // namespace Tegra
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