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surface: Correct format S8Z24

This commit is contained in:
Fernando Sahmkow 2019-06-14 16:40:04 -04:00 committed by ReinUsesLisp
parent 03d489dcf5
commit 082740d34d
4 changed files with 5 additions and 9 deletions
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2
src/video_core/engines/maxwell_dma.cpp
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@ -111,7 +111,7 @@ void MaxwellDMA::HandleCopy() {
memory_manager.WriteBlock(dest, write_buffer.data(), dst_size); memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
} else { } else {
ASSERT(regs.dst_params.BlockDepth() == 1); ASSERT(regs.dst_params.BlockDepth() == 0);
const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count; const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count;

4
src/video_core/surface.cpp
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@ -308,8 +308,8 @@ PixelFormat PixelFormatFromTextureFormat(Tegra::Texture::TextureFormat format,
return PixelFormat::Z32F; return PixelFormat::Z32F;
case Tegra::Texture::TextureFormat::Z16: case Tegra::Texture::TextureFormat::Z16:
return PixelFormat::Z16; return PixelFormat::Z16;
case Tegra::Texture::TextureFormat::Z24S8: case Tegra::Texture::TextureFormat::S8Z24:
return PixelFormat::Z24S8; return PixelFormat::S8Z24;
case Tegra::Texture::TextureFormat::ZF32_X24S8: case Tegra::Texture::TextureFormat::ZF32_X24S8:
return PixelFormat::Z32FS8; return PixelFormat::Z32FS8;
case Tegra::Texture::TextureFormat::DXT1: case Tegra::Texture::TextureFormat::DXT1:

4
src/video_core/texture_cache/texture_cache.h
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@ -534,10 +534,6 @@ private:
const auto host_ptr{memory_manager->GetPointer(gpu_addr)}; const auto host_ptr{memory_manager->GetPointer(gpu_addr)};
const auto cache_addr{ToCacheAddr(host_ptr)}; const auto cache_addr{ToCacheAddr(host_ptr)};
if (gpu_addr == 0x00000001682F0000ULL) {
LOG_CRITICAL(HW_GPU, "Here's the texture!");
}
// Step 0: guarantee a valid surface // Step 0: guarantee a valid surface
if (!cache_addr) { if (!cache_addr) {
// Return a null surface if it's invalid // Return a null surface if it's invalid

4
src/video_core/textures/texture.h
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@ -52,9 +52,9 @@ enum class TextureFormat : u32 {
DXT45 = 0x26, DXT45 = 0x26,
DXN1 = 0x27, DXN1 = 0x27,
DXN2 = 0x28, DXN2 = 0x28,
Z24S8 = 0x29, S8Z24 = 0x29,
X8Z24 = 0x2a, X8Z24 = 0x2a,
S8Z24 = 0x2b, Z24S8 = 0x2b,
X4V4Z24__COV4R4V = 0x2c, X4V4Z24__COV4R4V = 0x2c,
X4V4Z24__COV8R8V = 0x2d, X4V4Z24__COV8R8V = 0x2d,
V8Z24__COV4R12V = 0x2e, V8Z24__COV4R12V = 0x2e,