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Rasterizer: Document SignalFence & ReleaseFences and setup skeletons on Vulkan.

This commit is contained in:
Fernando Sahmkow 2020-02-18 13:24:38 -04:00
parent a081a7c855
commit 4adfc9bb08
5 changed files with 35 additions and 4 deletions

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@ -410,7 +410,6 @@ void Maxwell3D::ProcessQueryGet() {
StampQueryResult(regs.query.query_sequence, regs.query.query_get.short_query == 0); StampQueryResult(regs.query.query_sequence, regs.query.query_get.short_query == 0);
} }
break; break;
}
case Regs::QueryOperation::Acquire: case Regs::QueryOperation::Acquire:
// TODO(Blinkhawk): Under this operation, the GPU waits for the CPU to write a value that // TODO(Blinkhawk): Under this operation, the GPU waits for the CPU to write a value that
// matches the current payload. // matches the current payload.

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@ -81,9 +81,12 @@ void ThreadManager::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
} }
void ThreadManager::FlushRegion(VAddr addr, u64 size) { void ThreadManager::FlushRegion(VAddr addr, u64 size) {
if (!Settings::IsGPULevelExtreme()) {
return;
}
if (system.Renderer().Rasterizer().MustFlushRegion(addr, size)) { if (system.Renderer().Rasterizer().MustFlushRegion(addr, size)) {
u64 fence = PushCommand(FlushRegionCommand(addr, size)); u64 fence = PushCommand(FlushRegionCommand(addr, size));
while (fence < state.signaled_fence.load(std::memory_order_relaxed)) { while (fence > state.signaled_fence.load(std::memory_order_relaxed)) {
} }
} }
} }

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@ -49,9 +49,11 @@ public:
/// Records a GPU query and caches it /// Records a GPU query and caches it
virtual void Query(GPUVAddr gpu_addr, QueryType type, std::optional<u64> timestamp) = 0; virtual void Query(GPUVAddr gpu_addr, QueryType type, std::optional<u64> timestamp) = 0;
virtual void SignalFence(GPUVAddr addr, u32 value) {} /// Signal a GPU based fence
virtual void SignalFence(GPUVAddr addr, u32 value) = 0;
virtual void ReleaseFences() {} /// Release all pending fences.
virtual void ReleaseFences() = 0;
/// Notify rasterizer that all caches should be flushed to Switch memory /// Notify rasterizer that all caches should be flushed to Switch memory
virtual void FlushAll() = 0; virtual void FlushAll() = 0;

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@ -535,6 +535,7 @@ void RasterizerVulkan::OnCPUWrite(VAddr addr, u64 size) {
texture_cache.OnCPUWrite(addr, size); texture_cache.OnCPUWrite(addr, size);
pipeline_cache.InvalidateRegion(addr, size); pipeline_cache.InvalidateRegion(addr, size);
buffer_cache.OnCPUWrite(addr, size); buffer_cache.OnCPUWrite(addr, size);
query_cache.InvalidateRegion(addr, size);
} }
void RasterizerVulkan::SyncGuestHost() { void RasterizerVulkan::SyncGuestHost() {
@ -542,6 +543,30 @@ void RasterizerVulkan::SyncGuestHost() {
buffer_cache.SyncGuestHost(); buffer_cache.SyncGuestHost();
} }
void RasterizerVulkan::SignalFence(GPUVAddr addr, u32 value) {
auto& gpu{system.GPU()};
auto& memory_manager{gpu.MemoryManager()};
memory_manager.Write<u32>(addr, value);
/*
if (!gpu.IsAsync()) {
auto& memory_manager{gpu.MemoryManager()};
memory_manager.Write<u32>(addr, value);
return;
}
fence_manager.SignalFence(addr, value);
*/
}
void RasterizerVulkan::ReleaseFences() {
/*
auto& gpu{system.GPU()};
if (!gpu.IsAsync()) {
return;
}
fence_manager.WaitPendingFences();
*/
}
void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) { void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) {
FlushRegion(addr, size); FlushRegion(addr, size);
InvalidateRegion(addr, size); InvalidateRegion(addr, size);

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@ -122,6 +122,8 @@ public:
void InvalidateRegion(VAddr addr, u64 size) override; void InvalidateRegion(VAddr addr, u64 size) override;
void OnCPUWrite(VAddr addr, u64 size) override; void OnCPUWrite(VAddr addr, u64 size) override;
void SyncGuestHost() override; void SyncGuestHost() override;
void SignalFence(GPUVAddr addr, u32 value) override;
void ReleaseFences() override;
void FlushAndInvalidateRegion(VAddr addr, u64 size) override; void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
void FlushCommands() override; void FlushCommands() override;
void TickFrame() override; void TickFrame() override;