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Merge pull request #7407 from jam1garner/ic-ivau-instruction 

Add InstructionCacheOperationRaised handler for 'ic ivau' instruction
This commit is contained in:
Mai M 2021-11-21 23:16:36 -05:00 committed by GitHub
parent d20f91da11 4d9c9e567e
commit be238fb26a
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 20 additions and 0 deletions
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20
src/core/arm/dynarmic/arm_dynarmic_64.cpp
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@ -86,6 +86,26 @@ public:
num_instructions, MemoryReadCode(pc));
}
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
VAddr value) override {
switch (op) {
case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break;
}
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache();
break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break;
}
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
switch (exception) {
case Dynarmic::A64::Exception::WaitForInterrupt: