yuzu-emu
/
yuzu-mainline
Archived
1
0
Fork 0
Code

GPU: Added the TSC registers to the Maxwell3D register structure.

This commit is contained in:
Subv 2018-03-19 00:36:25 -05:00
parent cff7b29bba
commit dcae0c9a4f
1 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/video_core/engines/maxwell_3d.h
View File

@ -62,7 +62,20 @@ public:
union { union {
struct { struct {
INSERT_PADDING_WORDS(0x55D); INSERT_PADDING_WORDS(0x557);
struct {
u32 tsc_address_high;
u32 tsc_address_low;
u32 tsc_limit;
GPUVAddr TSCAddress() const {
return static_cast<GPUVAddr>(
(static_cast<GPUVAddr>(tsc_address_high) << 32) | tsc_address_low);
}
} tsc;
INSERT_PADDING_WORDS(0x3);
struct { struct {
u32 tic_address_high; u32 tic_address_high;
@ -278,6 +291,7 @@ private:
static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \ static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position") "Field " #field_name " has invalid position")
ASSERT_REG_POSITION(tsc, 0x557);
ASSERT_REG_POSITION(tic, 0x55D); ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(code_address, 0x582);
ASSERT_REG_POSITION(draw, 0x585); ASSERT_REG_POSITION(draw, 0x585);