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Merge pull request #554 from lioncash/cp15 

dyncom: Add more regs to MCR/MRC
This commit is contained in:
bunnei 2015-02-10 10:09:20 -05:00
parent eb83ac48aa 3eccc66abf
commit 695beb8dcf
2 changed files with 35 additions and 18 deletions
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49
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View File

@ -4725,20 +4725,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_cream->cp_num == 15) { if (inst_cream->cp_num == 15) {
if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
CP15_REG(CP15_MAIN_ID) = RD; CP15_REG(CP15_MAIN_ID) = RD;
} else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_CONTROL) = RD;
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) { } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
CP15_REG(CP15_AUXILIARY_CONTROL) = RD; CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) { } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD; CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
} else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_CONTROL) = RD;
} else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) { } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD; CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) { } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD; CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) { } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD; CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
} else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
} else if(CRn == MMU_CACHE_OPS){ } else if(CRn == MMU_CACHE_OPS){
//LOG_WARNING(Core_ARM11, "cache operations have not implemented."); //LOG_WARNING(Core_ARM11, "cache operations have not implemented.");
} else if(CRn == MMU_TLB_OPS){ } else if(CRn == MMU_TLB_OPS){
@ -4793,12 +4793,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
break; break;
} }
} else if(CRn == MMU_PID) { } else if(CRn == MMU_PID) {
if(OPCODE_2 == 0) if(OPCODE_2 == 0) {
CP15_REG(CP15_PID) = RD; CP15_REG(CP15_PID) = RD;
else if(OPCODE_2 == 1) } else if(OPCODE_2 == 1) {
CP15_REG(CP15_CONTEXT_ID) = RD; CP15_REG(CP15_CONTEXT_ID) = RD;
else if(OPCODE_2 == 3) { } else if (OPCODE_2 == 2) {
CP15_REG(CP15_THREAD_URO) = RD; CP15_REG(CP15_THREAD_UPRW) = RD;
} else if(OPCODE_2 == 3) {
if (InAPrivilegedMode(cpu))
CP15_REG(CP15_THREAD_URO) = RD;
} else if (OPCODE_2 == 4) {
if (InAPrivilegedMode(cpu))
CP15_REG(CP15_THREAD_PRW) = RD;
} else { } else {
LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn); LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn);
} }
@ -4886,31 +4892,40 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_cream->cp_num == 15) { if (inst_cream->cp_num == 15) {
if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
RD = cpu->CP15[CP15(CP15_MAIN_ID)]; RD = cpu->CP15[CP15(CP15_MAIN_ID)];
} else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_CONTROL)]; RD = cpu->CP15[CP15(CP15_CONTROL)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) { } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)]; RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) { } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)]; RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
} else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) { } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)]; RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
} else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) { } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_FAULT_STATUS)]; RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
} else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
} else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) { } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)]; RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
} else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
} else if (CRn == 13) { } else if (CRn == 13) {
if(OPCODE_2 == 0) if(OPCODE_2 == 0) {
RD = CP15_REG(CP15_PID); RD = CP15_REG(CP15_PID);
else if(OPCODE_2 == 1) } else if(OPCODE_2 == 1) {
RD = CP15_REG(CP15_CONTEXT_ID); RD = CP15_REG(CP15_CONTEXT_ID);
else if(OPCODE_2 == 3) { } else if (OPCODE_2 == 2) {
RD = CP15_REG(CP15_THREAD_UPRW);
} else if(OPCODE_2 == 3) {
RD = Memory::KERNEL_MEMORY_VADDR; RD = Memory::KERNEL_MEMORY_VADDR;
} else if (OPCODE_2 == 4) {
if (InAPrivilegedMode(cpu))
RD = CP15_REG(CP15_THREAD_PRW);
} else { } else {
LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn); LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn);
} }

4
src/core/arm/skyeye_common/arm_regformat.h
View File

@ -86,7 +86,9 @@ enum {
CP15_IFAR, CP15_IFAR,
CP15_PID, CP15_PID,
CP15_CONTEXT_ID, CP15_CONTEXT_ID,
CP15_THREAD_URO, CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
CP15_TLB_FAULT_ADDR, /* defined by SkyEye */ CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
CP15_TLB_FAULT_STATUS, /* defined by SkyEye */ CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
/* VFP registers */ /* VFP registers */