ARM_Interpreter/ARM_Interface: Fixed member variable naming to be consistent with style guide
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49dc2ce8ac
commit
0012802456
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@ -13,7 +13,7 @@
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class ARM_Interface : NonCopyable {
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public:
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ARM_Interface() {
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m_num_instructions = 0;
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num_instructions = 0;
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}
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~ARM_Interface() {
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@ -25,7 +25,7 @@ public:
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*/
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void Run(int num_instructions) {
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ExecuteInstructions(num_instructions);
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m_num_instructions += num_instructions;
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num_instructions += num_instructions;
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}
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/// Step CPU by one instruction
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@ -89,9 +89,9 @@ public:
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*/
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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/// Getter for m_num_instructions
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/// Getter for num_instructions
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u64 GetNumInstructions() {
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return m_num_instructions;
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return num_instructions;
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}
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protected:
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@ -104,6 +104,6 @@ protected:
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private:
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u64 m_num_instructions; ///< Number of instructions executed
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u64 num_instructions; ///< Number of instructions executed
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};
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@ -9,30 +9,30 @@ const static cpu_config_t s_arm11_cpu_info = {
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};
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ARM_Interpreter::ARM_Interpreter() {
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m_state = new ARMul_State;
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state = new ARMul_State;
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ARMul_EmulateInit();
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ARMul_NewState(m_state);
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ARMul_NewState(state);
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m_state->abort_model = 0;
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m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
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m_state->bigendSig = LOW;
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state->abort_model = 0;
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state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
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state->bigendSig = LOW;
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ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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m_state->lateabtSig = LOW;
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mmu_init(m_state);
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ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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state->lateabtSig = LOW;
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mmu_init(state);
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// Reset the core to initial state
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ARMul_Reset(m_state);
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m_state->NextInstr = 0;
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m_state->Emulate = 3;
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ARMul_Reset(state);
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state->NextInstr = 0;
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state->Emulate = 3;
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m_state->pc = m_state->Reg[15] = 0x00000000;
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m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->pc = state->Reg[15] = 0x00000000;
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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}
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ARM_Interpreter::~ARM_Interpreter() {
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delete m_state;
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delete state;
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}
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/**
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@ -40,7 +40,7 @@ ARM_Interpreter::~ARM_Interpreter() {
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* @param addr Address to set PC to
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*/
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void ARM_Interpreter::SetPC(u32 pc) {
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m_state->pc = m_state->Reg[15] = pc;
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state->pc = state->Reg[15] = pc;
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}
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/*
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@ -48,7 +48,7 @@ void ARM_Interpreter::SetPC(u32 pc) {
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* @return Returns current PC
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*/
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u32 ARM_Interpreter::GetPC() const {
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return m_state->pc;
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return state->pc;
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}
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/**
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@ -57,7 +57,7 @@ u32 ARM_Interpreter::GetPC() const {
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* @return Returns the value in the register
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*/
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u32 ARM_Interpreter::GetReg(int index) const {
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return m_state->Reg[index];
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return state->Reg[index];
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}
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/**
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@ -66,7 +66,7 @@ u32 ARM_Interpreter::GetReg(int index) const {
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* @param value Value to set register to
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*/
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void ARM_Interpreter::SetReg(int index, u32 value) {
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m_state->Reg[index] = value;
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state->Reg[index] = value;
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}
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/**
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@ -74,7 +74,7 @@ void ARM_Interpreter::SetReg(int index, u32 value) {
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* @return Returns the value of the CPSR register
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*/
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u32 ARM_Interpreter::GetCPSR() const {
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return m_state->Cpsr;
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return state->Cpsr;
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}
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/**
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@ -82,7 +82,7 @@ u32 ARM_Interpreter::GetCPSR() const {
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* @param cpsr Value to set CPSR to
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*/
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void ARM_Interpreter::SetCPSR(u32 cpsr) {
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m_state->Cpsr = cpsr;
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state->Cpsr = cpsr;
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}
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/**
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@ -90,7 +90,7 @@ void ARM_Interpreter::SetCPSR(u32 cpsr) {
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* @return Returns number of clock ticks
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*/
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u64 ARM_Interpreter::GetTicks() const {
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return ARMul_Time(m_state);
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return ARMul_Time(state);
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}
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/**
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@ -98,8 +98,8 @@ u64 ARM_Interpreter::GetTicks() const {
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* @param num_instructions Number of instructions to executes
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*/
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void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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m_state->NumInstrsToExecute = num_instructions;
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ARMul_Emulate32(m_state);
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state->NumInstrsToExecute = num_instructions;
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ARMul_Emulate32(state);
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}
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/**
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@ -108,16 +108,16 @@ void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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* @todo Do we need to save Reg[15] and NextInstr?
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*/
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void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, m_state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, m_state->ExtReg, sizeof(ctx.fpu_registers));
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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ctx.sp = m_state->Reg[13];
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ctx.lr = m_state->Reg[14];
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ctx.pc = m_state->pc;
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ctx.cpsr = m_state->Cpsr;
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ctx.sp = state->Reg[13];
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ctx.lr = state->Reg[14];
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ctx.pc = state->pc;
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ctx.cpsr = state->Cpsr;
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ctx.fpscr = m_state->VFP[1];
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ctx.fpexc = m_state->VFP[2];
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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}
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/**
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@ -126,14 +126,14 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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* @param Do we need to load Reg[15] and NextInstr?
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*/
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void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
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memcpy(m_state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(m_state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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m_state->Reg[13] = ctx.sp;
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m_state->Reg[14] = ctx.lr;
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m_state->pc = ctx.pc;
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m_state->Cpsr = ctx.cpsr;
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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state->pc = ctx.pc;
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state->Cpsr = ctx.cpsr;
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m_state->VFP[1] = ctx.fpscr;
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m_state->VFP[2] = ctx.fpexc;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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}
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@ -82,6 +82,6 @@ protected:
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private:
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ARMul_State* m_state;
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ARMul_State* state;
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};
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