arm: Remove TRUE/FALSE defines
- Removed the Debug parameter from ARMul_State since it isn't used. - Changed ARMul_CoProInit to a void function. It always returned true.
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@ -47,7 +47,7 @@ static unsigned int NoCoPro5W(ARMul_State* state, unsigned int a, ARMword b, ARM
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}
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// Install co-processor instruction handlers in this routine.
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unsigned int ARMul_CoProInit(ARMul_State* state)
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void ARMul_CoProInit(ARMul_State* state)
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{
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// Initialise tham all first.
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for (unsigned int i = 0; i < 16; i++)
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@ -71,11 +71,10 @@ unsigned int ARMul_CoProInit(ARMul_State* state)
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// No handlers below here.
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// Call all the initialisation routines.
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for (unsigned int i = 0; i < 16; i++)
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for (unsigned int i = 0; i < 16; i++) {
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if (state->CPInit[i])
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(state->CPInit[i]) (state);
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return TRUE;
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}
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}
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// Install co-processor finalisation routines in this routine.
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@ -63,24 +63,22 @@ void ARMul_EmulateInit()
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\***************************************************************************/
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ARMul_State* ARMul_NewState(ARMul_State* state)
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{
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unsigned i, j;
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memset (state, 0, sizeof (ARMul_State));
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state->Emulate = RUN;
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for (i = 0; i < 16; i++) {
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for (unsigned int i = 0; i < 16; i++) {
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state->Reg[i] = 0;
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for (j = 0; j < 7; j++)
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for (unsigned int j = 0; j < 7; j++)
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state->RegBank[j][i] = 0;
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}
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for (i = 0; i < 7; i++)
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for (unsigned int i = 0; i < 7; i++)
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state->Spsr[i] = 0;
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state->Mode = 0;
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state->Debug = FALSE;
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state->VectorCatch = 0;
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state->Aborted = FALSE;
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state->Reseted = FALSE;
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state->Aborted = false;
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state->Reseted = false;
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state->Inted = 3;
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state->LastInted = 3;
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@ -35,11 +35,6 @@
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#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
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#define BIT(s, n) ((s >> (n)) & 1)
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#ifndef FALSE
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#define FALSE 0
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#define TRUE 1
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#endif
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#define LOW 0
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#define HIGH 1
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#define LOWHIGH 1
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@ -135,7 +130,6 @@ struct ARMul_State
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unsigned char* CPData[16]; // Coprocessor data
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unsigned char const* CPRegWords[16]; // Map of coprocessor register sizes
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unsigned Debug; // Show instructions as they are executed
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unsigned NresetSig; // Reset the processor
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unsigned NfiqSig;
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unsigned NirqSig;
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@ -180,12 +174,12 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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*/
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unsigned lateabtSig;
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ARMword Vector; // Synthesize aborts in cycle modes
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ARMword Aborted; // Sticky flag for aborts
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ARMword Reseted; // Sticky flag for Reset
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bool Aborted; // Sticky flag for aborts
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bool Reseted; // Sticky flag for Reset
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ARMword Inted, LastInted; // Sticky flags for interrupts
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ARMword Base; // Extra hand for base writeback
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ARMword AbortAddr; // To keep track of Prefetch aborts
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ARMword Vector; // Synthesize aborts in cycle modes
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// For differentiating ARM core emulaiton.
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bool is_v4; // Are we emulating a v4 architecture (or higher)?
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@ -100,10 +100,10 @@ extern ARMword ARMul_ImmedTable[]; // Immediate DP LHS values.
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extern char ARMul_BitList[]; // Number of bits in a byte table.
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// Coprocessor support functions.
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extern unsigned ARMul_CoProInit (ARMul_State *);
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extern void ARMul_CoProExit (ARMul_State *);
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extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *,
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ARMul_CPExits *, ARMul_LDCs *, ARMul_STCs *,
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ARMul_MRCs *, ARMul_MCRs *, ARMul_MRRCs *, ARMul_MCRRs *,
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ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
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extern void ARMul_CoProDetach (ARMul_State *, unsigned);
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extern void ARMul_CoProInit(ARMul_State*);
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extern void ARMul_CoProExit(ARMul_State*);
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extern void ARMul_CoProAttach(ARMul_State*, unsigned, ARMul_CPInits*,
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ARMul_CPExits*, ARMul_LDCs*, ARMul_STCs*,
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ARMul_MRCs*, ARMul_MCRs*, ARMul_MRRCs*, ARMul_MCRRs*,
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ARMul_CDPs*, ARMul_CPReads*, ARMul_CPWrites*);
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extern void ARMul_CoProDetach(ARMul_State*, unsigned);
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