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armemu: Set the Q flag correctly for much of the other ops 

They were setting the old S flag.
This commit is contained in:
Lioncash 2014-12-23 09:59:35 -05:00
parent 79a7a432c5
commit 20fc5f2a35
1 changed files with 8 additions and 8 deletions
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16
src/core/arm/interpreter/armemu.cpp
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@ -1670,7 +1670,7 @@ mainswitch:
op1 *= op2; op1 *= op2;
//printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn); //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
if (AddOverflow(op1, Rn, op1 + Rn)) if (AddOverflow(op1, Rn, op1 + Rn))
SETS; SETQ;
state->Reg[BITS (16, 19)] = op1 + Rn; state->Reg[BITS (16, 19)] = op1 + Rn;
break; break;
} }
@ -1682,7 +1682,7 @@ mainswitch:
ARMword result = op1 + op2; ARMword result = op1 + op2;
if (AddOverflow(op1, op2, result)) { if (AddOverflow(op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
SETS; SETQ;
} }
state->Reg[BITS (12, 15)] = result; state->Reg[BITS (12, 15)] = result;
break; break;
@ -1795,7 +1795,7 @@ mainswitch:
ARMword Rn = state->Reg[BITS(12, 15)]; ARMword Rn = state->Reg[BITS(12, 15)];
if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn))) if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn)))
SETS; SETQ;
result += Rn; result += Rn;
} }
state->Reg[BITS (16, 19)] = (ARMword)result; state->Reg[BITS (16, 19)] = (ARMword)result;
@ -1811,7 +1811,7 @@ mainswitch:
if (SubOverflow if (SubOverflow
(op1, op2, result)) { (op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
SETS; SETQ;
} }
state->Reg[BITS (12, 15)] = result; state->Reg[BITS (12, 15)] = result;
@ -1934,13 +1934,13 @@ mainswitch:
if (AddOverflow if (AddOverflow
(op2, op2, op2d)) { (op2, op2, op2d)) {
SETS; SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
} }
result = op1 + op2d; result = op1 + op2d;
if (AddOverflow(op1, op2d, result)) { if (AddOverflow(op1, op2d, result)) {
SETS; SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
} }
@ -2053,13 +2053,13 @@ mainswitch:
ARMword result; ARMword result;
if (AddOverflow(op2, op2, op2d)) { if (AddOverflow(op2, op2, op2d)) {
SETS; SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
} }
result = op1 - op2d; result = op1 - op2d;
if (SubOverflow(op1, op2d, result)) { if (SubOverflow(op1, op2d, result)) {
SETS; SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
} }