vfp: Handle accesses to FPINST/FPINST2 system registers
Also has a side-benefit of correcting access to the FPEXC register.
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@ -59,6 +59,8 @@ enum {
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VFP_FPSID,
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VFP_FPSCR,
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VFP_FPEXC,
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VFP_FPINST,
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VFP_FPINST2,
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VFP_MVFR0,
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VFP_MVFR1,
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@ -33,6 +33,10 @@ unsigned VFPInit(ARMul_State* state)
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state->VFP[VFP_FPEXC] = 0;
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state->VFP[VFP_FPSCR] = 0;
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// ARM11 MPCore instruction register reset values.
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state->VFP[VFP_FPINST] = 0xEE000A00;
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state->VFP[VFP_FPINST2] = 0;
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// ARM11 MPCore feature register values.
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state->VFP[VFP_MVFR0] = 0x11111111;
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state->VFP[VFP_MVFR1] = 0;
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@ -40,18 +44,6 @@ unsigned VFPInit(ARMul_State* state)
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return 0;
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}
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void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
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{
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if (reg == 1)
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{
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state->VFP[VFP_FPSCR] = state->Reg[Rt];
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}
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else if (reg == 8)
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{
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state->VFP[VFP_FPEXC] = state->Reg[Rt];
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}
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}
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
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{
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if (to_arm)
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@ -36,10 +36,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
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u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
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void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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@ -995,7 +995,7 @@ VMOVBRS_INST:
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#ifdef VFP_INTERPRETER_STRUCT
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struct vmsr_inst {
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unsigned int reg;
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unsigned int Rd;
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unsigned int Rt;
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};
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#endif
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#ifdef VFP_INTERPRETER_TRANS
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@ -1009,7 +1009,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
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inst_base->br = NON_BRANCH;
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inst_cream->reg = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->Rt = BITS(inst, 12, 15);
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return inst_base;
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}
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@ -1017,15 +1017,30 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
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#ifdef VFP_INTERPRETER_IMPL
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VMSR_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
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and in privileged mode */
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/* Exceptions must be checked, according to v7 ref manual */
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CHECK_VFP_ENABLED;
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vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component;
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vmsr_inst* const inst_cream = (vmsr_inst*)inst_base->component;
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VMSR(cpu, inst_cream->reg, inst_cream->Rd);
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unsigned int reg = inst_cream->reg;
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unsigned int rt = inst_cream->Rt;
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if (reg == 1)
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{
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cpu->VFP[VFP_FPSCR] = cpu->Reg[rt];
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}
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else if (InAPrivilegedMode(cpu))
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{
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if (reg == 8)
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cpu->VFP[VFP_FPEXC] = cpu->Reg[rt];
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else if (reg == 9)
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cpu->VFP[VFP_FPINST] = cpu->Reg[rt];
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else if (reg == 10)
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cpu->VFP[VFP_FPINST2] = cpu->Reg[rt];
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(vmsr_inst));
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@ -1111,19 +1126,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
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#ifdef VFP_INTERPRETER_IMPL
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VMRS_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
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and in privileged mode */
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/* Exceptions must be checked, according to v7 ref manual */
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CHECK_VFP_ENABLED;
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vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
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vmrs_inst* const inst_cream = (vmrs_inst*)inst_base->component;
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if (inst_cream->reg == 1) /* FPSCR */
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unsigned int reg = inst_cream->reg;
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unsigned int rt = inst_cream->Rt;
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if (reg == 1) // FPSCR
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{
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if (inst_cream->Rt != 15)
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if (rt != 15)
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{
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cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSCR];
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cpu->Reg[rt] = cpu->VFP[VFP_FPSCR];
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}
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else
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{
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@ -1133,25 +1151,26 @@ VMRS_INST:
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cpu->VFlag = (cpu->VFP[VFP_FPSCR] >> 28) & 1;
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}
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}
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else
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else if (reg == 0)
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{
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switch (inst_cream->reg)
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{
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case 0:
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cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSID];
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break;
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case 6:
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cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_MVFR1];
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break;
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case 7:
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cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_MVFR0];
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break;
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case 8:
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cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPEXC];
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break;
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default:
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break;
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}
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cpu->Reg[rt] = cpu->VFP[VFP_FPSID];
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}
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else if (reg == 6)
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{
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cpu->Reg[rt] = cpu->VFP[VFP_MVFR1];
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}
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else if (reg == 7)
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{
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cpu->Reg[rt] = cpu->VFP[VFP_MVFR0];
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}
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else if (InAPrivilegedMode(cpu))
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{
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if (reg == 8)
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cpu->Reg[rt] = cpu->VFP[VFP_FPEXC];
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else if (reg == 9)
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cpu->Reg[rt] = cpu->VFP[VFP_FPINST];
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else if (reg == 10)
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cpu->Reg[rt] = cpu->VFP[VFP_FPINST2];
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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