Merge pull request #350 from lioncash/qops
Implement the rest of the UQ* ops.
This commit is contained in:
commit
3422d81f05
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@ -3249,12 +3249,44 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index)
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return inst_base;
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return inst_base;
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADD8"); }
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{
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADDSUBX"); }
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUB16"); }
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUBADDX"); }
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 21);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USADA8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USADA8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT"); }
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@ -6876,12 +6908,69 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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goto DISPATCH;
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goto DISPATCH;
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}
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}
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UQADD16_INST:
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UQADD8_INST:
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UQADD8_INST:
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UQADD16_INST:
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UQADDSUBX_INST:
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UQADDSUBX_INST:
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UQSUB16_INST:
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UQSUB8_INST:
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UQSUB8_INST:
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UQSUB16_INST:
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UQSUBADDX_INST:
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UQSUBADDX_INST:
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{
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u8 op2 = inst_cream->op2;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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u16 lo_val = 0;
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u16 hi_val = 0;
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// UQADD16
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if (op2 == 0x00) {
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lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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}
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// UQASX
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else if (op2 == 0x01) {
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lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
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}
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// UQSAX
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else if (op2 == 0x02) {
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lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
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}
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// UQSUB16
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else if (op2 == 0x03) {
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lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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}
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// UQADD8
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else if (op2 == 0x04) {
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lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) |
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ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8;
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hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) |
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ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8;
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}
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// UQSUB8
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else {
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lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) |
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ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8;
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hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) |
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ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8;
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}
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RD = ((lo_val & 0xFFFF) | hi_val << 16);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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USAD8_INST:
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USAD8_INST:
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USADA8_INST:
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USADA8_INST:
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USAT_INST:
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USAT_INST:
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@ -6117,26 +6117,55 @@ L_stm_s_takeabort:
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}
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}
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printf("Unhandled v6 insn: uasx/usax\n");
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printf("Unhandled v6 insn: uasx/usax\n");
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break;
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break;
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case 0x66:
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case 0x66: // UQADD16, UQASX, UQSAX, UQSUB16, UQADD8, and UQSUB8
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if ((instr & 0x0FF00FF0) == 0x06600FF0) { //uqsub8
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{
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u32 rd = (instr >> 12) & 0xF;
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const u8 rd_idx = BITS(12, 15);
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u32 rm = (instr >> 16) & 0xF;
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const u8 rm_idx = BITS(0, 3);
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u32 rn = (instr >> 0) & 0xF;
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const u8 rn_idx = BITS(16, 19);
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u32 subfrom = state->Reg[rm];
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const u8 op2 = BITS(5, 7);
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u32 tosub = state->Reg[rn];
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const u32 rm_val = state->Reg[rm_idx];
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const u32 rn_val = state->Reg[rn_idx];
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u8 b1 = (u8)((u8)(subfrom)-(u8)(tosub));
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u16 lo_val = 0;
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if (b1 > (u8)(subfrom)) b1 = 0;
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u16 hi_val = 0;
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u8 b2 = (u8)((u8)(subfrom >> 8) - (u8)(tosub >> 8));
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if (b2 > (u8)(subfrom >> 8)) b2 = 0;
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// UQADD16
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u8 b3 = (u8)((u8)(subfrom >> 16) - (u8)(tosub >> 16));
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if (op2 == 0x00) {
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if (b3 > (u8)(subfrom >> 16)) b3 = 0;
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lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
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u8 b4 = (u8)((u8)(subfrom >> 24) - (u8)(tosub >> 24));
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hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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if (b4 > (u8)(subfrom >> 24)) b4 = 0;
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}
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state->Reg[rd] = (u32)(b1 | b2 << 8 | b3 << 16 | b4 << 24);
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// UQASX
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else if (op2 == 0x01) {
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lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
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}
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// UQSAX
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else if (op2 == 0x02) {
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lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
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}
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// UQSUB16
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else if (op2 == 0x03) {
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lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF);
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hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
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}
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// UQADD8
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else if (op2 == 0x04) {
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lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) |
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ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8;
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hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) |
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ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8;
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}
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// UQSUB8
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else {
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lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) |
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ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8;
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hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) |
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ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8;
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}
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state->Reg[rd_idx] = ((lo_val & 0xFFFF) | hi_val << 16);
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return 1;
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return 1;
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} else {
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printf ("Unhandled v6 insn: uqsub16\n");
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}
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}
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break;
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break;
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case 0x67: // UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, and UHSUB8.
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case 0x67: // UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, and UHSUB8.
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@ -469,6 +469,47 @@ ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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ASSIGNV (SubOverflow (a, b, result));
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ASSIGNV (SubOverflow (a, b, result));
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}
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}
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/* 8-bit unsigned saturated addition */
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u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right)
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{
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u8 result = left + right;
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if (result < left)
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result = 0xFF;
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return result;
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}
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/* 16-bit unsigned saturated addition */
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u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right)
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{
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u16 result = left + right;
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if (result < left)
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result = 0xFFFF;
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return result;
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}
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/* 8-bit unsigned saturated subtraction */
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u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right)
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{
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if (left <= right)
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return 0;
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return left - right;
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}
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/* 16-bit unsigned saturated subtraction */
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u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right)
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{
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if (left <= right)
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return 0;
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return left - right;
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}
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/* This function does the work of generating the addresses used in an
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/* This function does the work of generating the addresses used in an
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LDC instruction. The code here is always post-indexed, it's up to the
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LDC instruction. The code here is always post-indexed, it's up to the
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caller to get the input address correct and to handle base register
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caller to get the input address correct and to handle base register
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@ -790,6 +790,11 @@ extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword);
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extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
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extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
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extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
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extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
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extern u8 ARMul_UnsignedSaturatedAdd8(u8, u8);
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extern u16 ARMul_UnsignedSaturatedAdd16(u16, u16);
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extern u8 ARMul_UnsignedSaturatedSub8(u8, u8);
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extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
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#define DIFF_LOG 0
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#define DIFF_LOG 0
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#define SAVE_LOG 0
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#define SAVE_LOG 0
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