dyncom: Implement SADD8/SSUB8
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08b6cf778d
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4e2cb06b81
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@ -2171,8 +2171,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index)
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}
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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@ -2190,10 +2189,27 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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return INTERPRETER_TRANSLATE(sadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst));
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@ -2408,15 +2424,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst));
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@ -5039,6 +5047,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SADD8_INST:
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SSUB8_INST:
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SADD16_INST:
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SADDSUBX_INST:
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SSUBADDX_INST:
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@ -5046,7 +5055,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u8 op2 = inst_cream->op2;
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if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
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const s16 rn_lo = (RN & 0xFFFF);
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const s16 rn_hi = ((RN >> 16) & 0xFFFF);
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const s16 rm_lo = (RM & 0xFFFF);
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@ -5061,17 +5072,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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hi_result = (rn_hi + rm_hi);
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}
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// SASX
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else if (inst_cream->op2 == 0x01) {
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else if (op2 == 0x01) {
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lo_result = (rn_lo - rm_hi);
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hi_result = (rn_hi + rm_lo);
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}
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// SSAX
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else if (inst_cream->op2 == 0x02) {
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else if (op2 == 0x02) {
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lo_result = (rn_lo + rm_hi);
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hi_result = (rn_hi - rm_lo);
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}
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// SSUB16
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else if (inst_cream->op2 == 0x03) {
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else if (op2 == 0x03) {
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lo_result = (rn_lo - rm_lo);
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hi_result = (rn_hi - rm_hi);
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}
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@ -5094,6 +5105,48 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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cpu->Cpsr &= ~(1 << 19);
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}
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}
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else if (op2 == 0x04 || op2 == 0x07) {
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s32 lo_val1, lo_val2;
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s32 hi_val1, hi_val2;
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// SADD8
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if (op2 == 0x04) {
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lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF);
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lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF);
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hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF);
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hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF);
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}
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// SSUB8
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else {
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lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF);
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lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF);
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hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF);
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hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF);
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}
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RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24));
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if (lo_val1 >= 0)
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cpu->Cpsr |= (1 << 16);
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else
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cpu->Cpsr &= ~(1 << 16);
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if (lo_val2 >= 0)
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cpu->Cpsr |= (1 << 17);
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else
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cpu->Cpsr &= ~(1 << 17);
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if (hi_val1 >= 0)
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cpu->Cpsr |= (1 << 18);
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else
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cpu->Cpsr &= ~(1 << 18);
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if (hi_val2 >= 0)
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cpu->Cpsr |= (1 << 19);
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else
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cpu->Cpsr &= ~(1 << 19);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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@ -5407,7 +5460,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SSUB8_INST:
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STC_INST:
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{
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// Instruction not implemented
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