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Merge pull request #1618 from MerryMage/one-step 

Prevent cache overflow when single stepping
This commit is contained in:
Mathew Maidment 2016-03-31 11:00:42 -04:00
parent 67c982be1b cbba0bec7c
commit 80c16961ae
1 changed files with 57 additions and 26 deletions
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81
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -36,7 +36,8 @@ enum {
CALL = (1 << 4), CALL = (1 << 4),
RET = (1 << 5), RET = (1 << 5),
END_OF_PAGE = (1 << 6), END_OF_PAGE = (1 << 6),
THUMB = (1 << 7) THUMB = (1 << 7),
SINGLE_STEP = (1 << 8)
}; };
#define RM BITS(sht_oper, 0, 3) #define RM BITS(sht_oper, 0, 3)
@ -3466,28 +3467,10 @@ enum {
MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64)); MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) { static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, ARM_INST_PTR& inst_base) {
Common::Profiling::ScopeTimer timer_decode(profile_decode); unsigned int inst_size = 4;
MICROPROFILE_SCOPE(DynCom_Decode); unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
// Decode instruction, get index
// Allocate memory and init InsCream
// Go on next, until terminal instruction
// Save start addr of basicblock in CreamCache
ARM_INST_PTR inst_base = nullptr;
unsigned int inst, inst_size = 4;
int idx;
int ret = NON_BRANCH;
int size = 0; // instruction size of basic block
bb_start = top;
u32 phys_addr = addr;
u32 pc_start = cpu->Reg[15];
while (ret == NON_BRANCH) {
inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
size++;
// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
if (cpu->TFlag) { if (cpu->TFlag) {
u32 arm_inst; u32 arm_inst;
@ -3495,11 +3478,12 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
// We have translated the Thumb branch instruction in the Thumb decoder // We have translated the Thumb branch instruction in the Thumb decoder
if (state == ThumbDecodeStatus::BRANCH) { if (state == ThumbDecodeStatus::BRANCH) {
goto translated; return inst_size;
} }
inst = arm_inst; inst = arm_inst;
} }
int idx;
if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst); LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
@ -3508,7 +3492,30 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
} }
inst_base = arm_instruction_trans[idx](inst, idx); inst_base = arm_instruction_trans[idx](inst, idx);
translated: return inst_size;
}
static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) {
Common::Profiling::ScopeTimer timer_decode(profile_decode);
MICROPROFILE_SCOPE(DynCom_Decode);
// Decode instruction, get index
// Allocate memory and init InsCream
// Go on next, until terminal instruction
// Save start addr of basicblock in CreamCache
ARM_INST_PTR inst_base = nullptr;
int ret = NON_BRANCH;
int size = 0; // instruction size of basic block
bb_start = top;
u32 phys_addr = addr;
u32 pc_start = cpu->Reg[15];
while (ret == NON_BRANCH) {
unsigned int inst_size = InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
size++;
phys_addr += inst_size; phys_addr += inst_size;
if ((phys_addr & 0xfff) == 0) { if ((phys_addr & 0xfff) == 0) {
@ -3522,6 +3529,27 @@ translated:
return KEEP_GOING; return KEEP_GOING;
} }
static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) {
Common::Profiling::ScopeTimer timer_decode(profile_decode);
MICROPROFILE_SCOPE(DynCom_Decode);
ARM_INST_PTR inst_base = nullptr;
bb_start = top;
u32 phys_addr = addr;
u32 pc_start = cpu->Reg[15];
InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
if (inst_base->br == NON_BRANCH) {
inst_base->br = SINGLE_STEP;
}
cpu->instruction_cache[pc_start] = bb_start;
return KEEP_GOING;
}
static int clz(unsigned int x) { static int clz(unsigned int x) {
int n; int n;
if (x == 0) return (32); if (x == 0) return (32);
@ -3871,8 +3899,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
auto itr = cpu->instruction_cache.find(cpu->Reg[15]); auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
if (itr != cpu->instruction_cache.end()) { if (itr != cpu->instruction_cache.end()) {
ptr = itr->second; ptr = itr->second;
} else if (cpu->NumInstrsToExecute != 1) {
if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
goto END;
} else { } else {
if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
goto END; goto END;
} }