armemu: Fix construction of the CPSR
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2188af4a65
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8e2accd974
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@ -5877,6 +5877,8 @@ L_stm_s_takeabort:
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state->Cpsr &= ~(1 << 18);
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state->Cpsr &= ~(1 << 19);
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}
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ARMul_CPSRAltered(state);
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return 1;
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}
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// SADD8/SSUB8
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@ -5948,6 +5950,7 @@ L_stm_s_takeabort:
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state->Cpsr &= ~(1 << 19);
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}
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ARMul_CPSRAltered(state);
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state->Reg[rd_idx] = (lo_val1 | lo_val2 << 8 | hi_val1 << 16 | hi_val2 << 24);
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return 1;
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}
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@ -6024,15 +6027,33 @@ L_stm_s_takeabort:
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if ((instr & 0x0F0) == 0x070) { // USUB16
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h1 = ((u16)from - (u16)to);
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h2 = ((u16)(from >> 16) - (u16)(to >> 16));
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if (!(h1 & 0xffff0000)) state->Cpsr |= (3 << 16);
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if (!(h2 & 0xffff0000)) state->Cpsr |= (3 << 18);
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if (!(h1 & 0xffff0000))
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state->Cpsr |= (3 << 16);
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else
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state->Cpsr &= ~(3 << 16);
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if (!(h2 & 0xffff0000))
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state->Cpsr |= (3 << 18);
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else
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state->Cpsr &= ~(3 << 18);
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}
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else { // UADD16
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h1 = ((u16)from + (u16)to);
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h2 = ((u16)(from >> 16) + (u16)(to >> 16));
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if (h1 & 0xffff0000) state->Cpsr |= (3 << 16);
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if (h2 & 0xffff0000) state->Cpsr |= (3 << 18);
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if (h1 & 0xffff0000)
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state->Cpsr |= (3 << 16);
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else
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state->Cpsr &= ~(3 << 16);
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if (h2 & 0xffff0000)
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state->Cpsr |= (3 << 18);
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else
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state->Cpsr &= ~(3 << 18);
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}
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ARMul_CPSRAltered(state);
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state->Reg[rd] = (u32)((h1 & 0xffff) | ((h2 & 0xffff) << 16));
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return 1;
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}
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@ -6045,10 +6066,26 @@ L_stm_s_takeabort:
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b2 = ((u8)(from >> 8) - (u8)(to >> 8));
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b3 = ((u8)(from >> 16) - (u8)(to >> 16));
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b4 = ((u8)(from >> 24) - (u8)(to >> 24));
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if (!(b1 & 0xffffff00)) state->Cpsr |= (1 << 16);
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if (!(b2 & 0xffffff00)) state->Cpsr |= (1 << 17);
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if (!(b3 & 0xffffff00)) state->Cpsr |= (1 << 18);
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if (!(b4 & 0xffffff00)) state->Cpsr |= (1 << 19);
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if (!(b1 & 0xffffff00))
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state->Cpsr |= (1 << 16);
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else
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state->Cpsr &= ~(1 << 16);
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if (!(b2 & 0xffffff00))
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state->Cpsr |= (1 << 17);
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else
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state->Cpsr &= ~(1 << 17);
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if (!(b3 & 0xffffff00))
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state->Cpsr |= (1 << 18);
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else
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state->Cpsr &= ~(1 << 18);
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if (!(b4 & 0xffffff00))
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state->Cpsr |= (1 << 19);
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else
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state->Cpsr &= ~(1 << 19);
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}
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else { // UADD8
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b1 = ((u8)from + (u8)to);
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@ -6071,13 +6108,13 @@ L_stm_s_takeabort:
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else
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state->Cpsr &= ~(1 << 18);
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if (b4 & 0xffffff00)
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state->Cpsr |= (1 << 19);
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else
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state->Cpsr &= ~(1 << 19);
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}
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ARMul_CPSRAltered(state);
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state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
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return 1;
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}
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@ -227,8 +227,9 @@ ARMul_CPSRAltered (ARMul_State * state)
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//state->Cpsr &= ~CBIT;
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ASSIGNV ((state->Cpsr & VBIT) != 0);
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//state->Cpsr &= ~VBIT;
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ASSIGNS ((state->Cpsr & SBIT) != 0);
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//state->Cpsr &= ~SBIT;
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ASSIGNQ ((state->Cpsr & QBIT) != 0);
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//state->Cpsr &= ~QBIT;
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state->GEFlag = (state->Cpsr & 0x000F0000);
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#ifdef MODET
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ASSIGNT ((state->Cpsr & TBIT) != 0);
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//state->Cpsr &= ~TBIT;
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@ -198,7 +198,7 @@ struct ARMul_State
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//ARMword translate_pc;
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/* add armv6 flags dyf:2010-08-09 */
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ARMword GEFlag, EFlag, AFlag, QFlags;
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ARMword GEFlag, EFlag, AFlag, QFlag;
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//chy:2003-08-19, used in arm v5e|xscale
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ARMword SFlag;
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#ifdef MODET
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@ -34,7 +34,7 @@
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#define ZBIT (1L << 30)
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#define CBIT (1L << 29)
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#define VBIT (1L << 28)
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#define SBIT (1L << 27)
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#define QBIT (1L << 27)
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#define IBIT (1L << 7)
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#define FBIT (1L << 6)
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#define IFBITS (3L << 6)
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@ -156,13 +156,14 @@
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#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
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#define R15MODE (state->Reg[15] & R15MODEBITS)
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#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
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#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (QFLAG << 27))
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#define EINT (IFFLAGS << 6)
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#define ER15INT (IFFLAGS << 26)
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#define EMODE (state->Mode)
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#define EGEBITS (state->GEFlag & 0x000F0000)
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#ifdef MODET
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#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
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#define CPSR (ECC | EGEBITS | (EFLAG << 9) | (AFLAG << 8) | EINT | (TFLAG << 5) | EMODE)
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#else
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#define CPSR (ECC | EINT | EMODE)
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#endif
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