Merge pull request #336 from lioncash/datqflag
armemu: Correctly set the Q flag for a bunch of ops.
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commit
a7893adf20
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@ -1670,7 +1670,7 @@ mainswitch:
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op1 *= op2;
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//printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
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if (AddOverflow(op1, Rn, op1 + Rn))
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SETS;
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SETQ;
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state->Reg[BITS (16, 19)] = op1 + Rn;
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break;
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}
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@ -1682,7 +1682,7 @@ mainswitch:
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ARMword result = op1 + op2;
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if (AddOverflow(op1, op2, result)) {
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result = POS (result) ? 0x80000000 : 0x7fffffff;
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SETS;
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SETQ;
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}
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state->Reg[BITS (12, 15)] = result;
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break;
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@ -1795,7 +1795,7 @@ mainswitch:
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ARMword Rn = state->Reg[BITS(12, 15)];
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if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn)))
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SETS;
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SETQ;
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result += Rn;
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}
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state->Reg[BITS (16, 19)] = (ARMword)result;
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@ -1811,7 +1811,7 @@ mainswitch:
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if (SubOverflow
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(op1, op2, result)) {
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result = POS (result) ? 0x80000000 : 0x7fffffff;
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SETS;
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SETQ;
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}
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state->Reg[BITS (12, 15)] = result;
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@ -1934,13 +1934,13 @@ mainswitch:
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if (AddOverflow
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(op2, op2, op2d)) {
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SETS;
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SETQ;
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op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
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}
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result = op1 + op2d;
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if (AddOverflow(op1, op2d, result)) {
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SETS;
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SETQ;
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result = POS (result) ? 0x80000000 : 0x7fffffff;
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}
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@ -2053,13 +2053,13 @@ mainswitch:
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ARMword result;
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if (AddOverflow(op2, op2, op2d)) {
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SETS;
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SETQ;
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op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
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}
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result = op1 - op2d;
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if (SubOverflow(op1, op2d, result)) {
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SETS;
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SETQ;
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result = POS (result) ? 0x80000000 : 0x7fffffff;
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}
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@ -6478,22 +6478,28 @@ L_stm_s_takeabort:
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const s16 rn_lo = (rn_val & 0xFFFF);
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const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
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// SMUAD
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if ((instr & 0xf0d0) == 0xf010) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi);
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const u32 product1 = (rn_lo * rm_lo);
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const u32 product2 = (rn_hi * rm_hi);
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// SMUAD and SMLAD
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if (BIT(6) == 0) {
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state->Reg[rd_idx] = product1 + product2;
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if (BITS(12, 15) != 15) {
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state->Reg[rd_idx] += state->Reg[ra_idx];
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ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
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}
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ARMul_AddOverflowQ(state, product1, product2);
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}
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// SMUSD
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else if ((instr & 0xf0d0) == 0xf050) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
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}
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// SMLAD
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else if ((instr & 0xd0) == 0x10) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
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}
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// SMLSD
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// SMUSD and SMLSD
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else {
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state->Reg[rd_idx] = ((rn_lo * rm_lo) - (rn_hi * rm_hi)) + (s32)state->Reg[ra_idx];
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state->Reg[rd_idx] = product1 - product2;
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if (BITS(12, 15) != 15)
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state->Reg[rd_idx] += state->Reg[ra_idx];
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}
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return 1;
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}
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break;
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@ -444,6 +444,14 @@ ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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ASSIGNV (AddOverflow (a, b, result));
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}
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/* Assigns the Q flag if the given result is considered an overflow from the addition of a and b */
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void ARMul_AddOverflowQ(ARMul_State* state, ARMword a, ARMword b)
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{
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u32 result = a + b;
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if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)
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SETQ;
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}
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/* Assigns the C flag after an subtraction of a and b to give result. */
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void
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@ -602,6 +602,7 @@ extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
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extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
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extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddOverflowQ(ARMul_State*, ARMword, ARMword);
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extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
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extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
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