VideoCore: Split rasterizer regs from Regs struct
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97e06b0a0d
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@ -359,7 +359,7 @@ void GraphicsVertexShaderWidget::DumpShader() {
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auto& config = Pica::g_state.regs.vs;
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Pica::DebugUtils::DumpShader(filename.toStdString(), config, setup,
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Pica::g_state.regs.vs_output_attributes);
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Pica::g_state.regs.rasterizer.vs_output_attributes);
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}
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GraphicsVertexShaderWidget::GraphicsVertexShaderWidget(
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@ -32,6 +32,7 @@ set(HEADERS
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primitive_assembly.h
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rasterizer.h
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rasterizer_interface.h
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regs_rasterizer.h
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renderer_base.h
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renderer_opengl/gl_rasterizer.h
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renderer_opengl/gl_rasterizer_cache.h
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@ -64,10 +64,10 @@ static void InitScreenCoordinates(Vertex& vtx) {
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} viewport;
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const auto& regs = g_state.regs;
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viewport.halfsize_x = float24::FromRaw(regs.viewport_size_x);
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viewport.halfsize_y = float24::FromRaw(regs.viewport_size_y);
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viewport.offset_x = float24::FromFloat32(static_cast<float>(regs.viewport_corner.x));
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viewport.offset_y = float24::FromFloat32(static_cast<float>(regs.viewport_corner.y));
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viewport.halfsize_x = float24::FromRaw(regs.rasterizer.viewport_size_x);
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viewport.halfsize_y = float24::FromRaw(regs.rasterizer.viewport_size_y);
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viewport.offset_x = float24::FromFloat32(static_cast<float>(regs.rasterizer.viewport_corner.x));
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viewport.offset_y = float24::FromFloat32(static_cast<float>(regs.rasterizer.viewport_corner.y));
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float24 inv_w = float24::FromFloat32(1.f) / vtx.pos.w;
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vtx.color *= inv_w;
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@ -165,7 +165,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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};
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g_state.primitive_assembler.SubmitVertex(
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Shader::OutputVertex::FromAttributeBuffer(regs, output), AddTriangle);
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Shader::OutputVertex::FromAttributeBuffer(regs.rasterizer, output),
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AddTriangle);
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}
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}
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}
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@ -295,7 +296,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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shader_unit.WriteOutput(regs.vs, output);
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// Retrieve vertex from register data
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output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs, output);
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output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs.rasterizer, output);
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if (is_indexed) {
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vertex_cache[vertex_cache_pos] = output_vertex;
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@ -90,7 +90,7 @@ namespace DebugUtils {
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void DumpShader(const std::string& filename, const Regs::ShaderConfig& config,
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const Shader::ShaderSetup& setup,
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const Regs::VSOutputAttributes* output_attributes) {
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const RasterizerRegs::VSOutputAttributes* output_attributes) {
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struct StuffToWrite {
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const u8* pointer;
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u32 size;
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@ -129,7 +129,7 @@ void DumpShader(const std::string& filename, const Regs::ShaderConfig& config,
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// This is put into a try-catch block to make sure we notice unknown configurations.
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std::vector<OutputRegisterInfo> output_info_table;
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for (unsigned i = 0; i < 7; ++i) {
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using OutputAttributes = Pica::Regs::VSOutputAttributes;
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using OutputAttributes = Pica::RasterizerRegs::VSOutputAttributes;
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// TODO: It's still unclear how the attribute components map to the register!
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// Once we know that, this code probably will not make much sense anymore.
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@ -184,7 +184,7 @@ namespace DebugUtils {
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void DumpShader(const std::string& filename, const Regs::ShaderConfig& config,
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const Shader::ShaderSetup& setup,
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const Regs::VSOutputAttributes* output_attributes);
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const RasterizerRegs::VSOutputAttributes* output_attributes);
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// Utility class to log Pica commands.
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struct PicaTrace {
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@ -18,6 +18,7 @@
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/vector_math.h"
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#include "video_core/regs_rasterizer.h"
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namespace Pica {
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@ -44,121 +45,10 @@ namespace Pica {
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#endif // _MSC_VER
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struct Regs {
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INSERT_PADDING_WORDS(0x10);
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u32 trigger_irq;
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INSERT_PADDING_WORDS(0x2f);
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enum class CullMode : u32 {
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// Select which polygons are considered to be "frontfacing".
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KeepAll = 0,
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KeepClockWise = 1,
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KeepCounterClockWise = 2,
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// TODO: What does the third value imply?
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};
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union {
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BitField<0, 2, CullMode> cull_mode;
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};
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BitField<0, 24, u32> viewport_size_x;
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 24, u32> viewport_size_y;
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INSERT_PADDING_WORDS(0x9);
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_near_plane; // float24
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BitField<0, 3, u32> vs_output_total;
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union VSOutputAttributes {
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// Maps components of output vertex attributes to semantics
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enum Semantic : u32 {
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POSITION_X = 0,
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POSITION_Y = 1,
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POSITION_Z = 2,
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POSITION_W = 3,
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QUATERNION_X = 4,
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QUATERNION_Y = 5,
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QUATERNION_Z = 6,
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QUATERNION_W = 7,
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COLOR_R = 8,
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COLOR_G = 9,
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COLOR_B = 10,
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COLOR_A = 11,
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TEXCOORD0_U = 12,
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TEXCOORD0_V = 13,
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TEXCOORD1_U = 14,
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TEXCOORD1_V = 15,
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TEXCOORD0_W = 16,
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VIEW_X = 18,
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VIEW_Y = 19,
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VIEW_Z = 20,
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TEXCOORD2_U = 22,
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TEXCOORD2_V = 23,
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INVALID = 31,
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};
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BitField<0, 5, Semantic> map_x;
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BitField<8, 5, Semantic> map_y;
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BitField<16, 5, Semantic> map_z;
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BitField<24, 5, Semantic> map_w;
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} vs_output_attributes[7];
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INSERT_PADDING_WORDS(0xe);
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enum class ScissorMode : u32 {
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Disabled = 0,
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Exclude = 1, // Exclude pixels inside the scissor box
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Include = 3 // Exclude pixels outside the scissor box
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};
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struct {
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BitField<0, 2, ScissorMode> mode;
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union {
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BitField<0, 16, u32> x1;
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BitField<16, 16, u32> y1;
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};
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union {
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BitField<0, 16, u32> x2;
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BitField<16, 16, u32> y2;
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};
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} scissor_test;
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union {
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BitField<0, 10, s32> x;
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BitField<16, 10, s32> y;
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} viewport_corner;
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INSERT_PADDING_WORDS(0x1);
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// TODO: early depth
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INSERT_PADDING_WORDS(0x1);
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INSERT_PADDING_WORDS(0x2);
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enum DepthBuffering : u32 {
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WBuffering = 0,
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ZBuffering = 1,
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};
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BitField<0, 1, DepthBuffering> depthmap_enable;
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INSERT_PADDING_WORDS(0x12);
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RasterizerRegs rasterizer;
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struct TextureConfig {
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enum TextureType : u32 {
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@ -1338,16 +1228,19 @@ private:
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(trigger_irq, 0x10);
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ASSERT_REG_POSITION(cull_mode, 0x40);
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ASSERT_REG_POSITION(viewport_size_x, 0x41);
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ASSERT_REG_POSITION(viewport_size_y, 0x43);
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ASSERT_REG_POSITION(viewport_depth_range, 0x4d);
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ASSERT_REG_POSITION(viewport_depth_near_plane, 0x4e);
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ASSERT_REG_POSITION(vs_output_attributes[0], 0x50);
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ASSERT_REG_POSITION(vs_output_attributes[1], 0x51);
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ASSERT_REG_POSITION(scissor_test, 0x65);
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ASSERT_REG_POSITION(viewport_corner, 0x68);
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ASSERT_REG_POSITION(depthmap_enable, 0x6D);
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ASSERT_REG_POSITION(rasterizer, 0x40);
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ASSERT_REG_POSITION(rasterizer.cull_mode, 0x40);
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ASSERT_REG_POSITION(rasterizer.viewport_size_x, 0x41);
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ASSERT_REG_POSITION(rasterizer.viewport_size_y, 0x43);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_range, 0x4d);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_near_plane, 0x4e);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[0], 0x50);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[1], 0x51);
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ASSERT_REG_POSITION(rasterizer.scissor_test, 0x65);
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ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
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ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
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ASSERT_REG_POSITION(texture0_enable, 0x80);
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ASSERT_REG_POSITION(texture0, 0x81);
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ASSERT_REG_POSITION(texture0_format, 0x8e);
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@ -327,14 +327,14 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
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ScreenToRasterizerCoordinates(v1.screenpos),
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ScreenToRasterizerCoordinates(v2.screenpos)};
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if (regs.cull_mode == Regs::CullMode::KeepAll) {
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if (regs.rasterizer.cull_mode == RasterizerRegs::CullMode::KeepAll) {
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// Make sure we always end up with a triangle wound counter-clockwise
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if (!reversed && SignedArea(vtxpos[0].xy(), vtxpos[1].xy(), vtxpos[2].xy()) <= 0) {
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ProcessTriangleInternal(v0, v2, v1, true);
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return;
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}
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} else {
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if (!reversed && regs.cull_mode == Regs::CullMode::KeepClockWise) {
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if (!reversed && regs.rasterizer.cull_mode == RasterizerRegs::CullMode::KeepClockWise) {
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// Reverse vertex order and use the CCW code path.
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ProcessTriangleInternal(v0, v2, v1, true);
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return;
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@ -351,13 +351,13 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
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u16 max_y = std::max({vtxpos[0].y, vtxpos[1].y, vtxpos[2].y});
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// Convert the scissor box coordinates to 12.4 fixed point
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u16 scissor_x1 = (u16)(regs.scissor_test.x1 << 4);
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u16 scissor_y1 = (u16)(regs.scissor_test.y1 << 4);
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u16 scissor_x1 = (u16)(regs.rasterizer.scissor_test.x1 << 4);
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u16 scissor_y1 = (u16)(regs.rasterizer.scissor_test.y1 << 4);
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// x2,y2 have +1 added to cover the entire sub-pixel area
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u16 scissor_x2 = (u16)((regs.scissor_test.x2 + 1) << 4);
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u16 scissor_y2 = (u16)((regs.scissor_test.y2 + 1) << 4);
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u16 scissor_x2 = (u16)((regs.rasterizer.scissor_test.x2 + 1) << 4);
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u16 scissor_y2 = (u16)((regs.rasterizer.scissor_test.y2 + 1) << 4);
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if (regs.scissor_test.mode == Regs::ScissorMode::Include) {
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if (regs.rasterizer.scissor_test.mode == RasterizerRegs::ScissorMode::Include) {
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// Calculate the new bounds
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min_x = std::max(min_x, scissor_x1);
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min_y = std::max(min_y, scissor_y1);
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@ -411,7 +411,7 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
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// Do not process the pixel if it's inside the scissor box and the scissor mode is set
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// to Exclude
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if (regs.scissor_test.mode == Regs::ScissorMode::Exclude) {
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if (regs.rasterizer.scissor_test.mode == RasterizerRegs::ScissorMode::Exclude) {
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if (x >= scissor_x1 && x < scissor_x2 && y >= scissor_y1 && y < scissor_y2)
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continue;
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}
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@ -441,12 +441,14 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
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// Not fully accurate. About 3 bits in precision are missing.
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// Z-Buffer (z / w * scale + offset)
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float depth_scale = float24::FromRaw(regs.viewport_depth_range).ToFloat32();
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float depth_offset = float24::FromRaw(regs.viewport_depth_near_plane).ToFloat32();
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float depth_scale = float24::FromRaw(regs.rasterizer.viewport_depth_range).ToFloat32();
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float depth_offset =
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float24::FromRaw(regs.rasterizer.viewport_depth_near_plane).ToFloat32();
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float depth = interpolated_z_over_w * depth_scale + depth_offset;
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// Potentially switch to W-Buffer
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if (regs.depthmap_enable == Pica::Regs::DepthBuffering::WBuffering) {
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if (regs.rasterizer.depthmap_enable ==
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Pica::RasterizerRegs::DepthBuffering::WBuffering) {
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// W-Buffer (z * scale + w * offset = (z / w * scale + offset) * w)
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depth *= interpolated_w_inverse.ToFloat32() * wsum;
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}
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@ -0,0 +1,129 @@
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// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Pica {
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struct RasterizerRegs {
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enum class CullMode : u32 {
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// Select which polygons are considered to be "frontfacing".
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KeepAll = 0,
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KeepClockWise = 1,
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KeepCounterClockWise = 2,
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// TODO: What does the third value imply?
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};
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union {
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BitField<0, 2, CullMode> cull_mode;
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};
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BitField<0, 24, u32> viewport_size_x;
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 24, u32> viewport_size_y;
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INSERT_PADDING_WORDS(0x9);
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_near_plane; // float24
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BitField<0, 3, u32> vs_output_total;
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union VSOutputAttributes {
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// Maps components of output vertex attributes to semantics
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enum Semantic : u32 {
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POSITION_X = 0,
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POSITION_Y = 1,
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POSITION_Z = 2,
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POSITION_W = 3,
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QUATERNION_X = 4,
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QUATERNION_Y = 5,
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QUATERNION_Z = 6,
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QUATERNION_W = 7,
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COLOR_R = 8,
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COLOR_G = 9,
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COLOR_B = 10,
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COLOR_A = 11,
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TEXCOORD0_U = 12,
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TEXCOORD0_V = 13,
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TEXCOORD1_U = 14,
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TEXCOORD1_V = 15,
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TEXCOORD0_W = 16,
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VIEW_X = 18,
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VIEW_Y = 19,
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VIEW_Z = 20,
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TEXCOORD2_U = 22,
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TEXCOORD2_V = 23,
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INVALID = 31,
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};
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BitField<0, 5, Semantic> map_x;
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BitField<8, 5, Semantic> map_y;
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BitField<16, 5, Semantic> map_z;
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BitField<24, 5, Semantic> map_w;
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} vs_output_attributes[7];
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INSERT_PADDING_WORDS(0xe);
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enum class ScissorMode : u32 {
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Disabled = 0,
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Exclude = 1, // Exclude pixels inside the scissor box
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Include = 3 // Exclude pixels outside the scissor box
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};
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struct {
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BitField<0, 2, ScissorMode> mode;
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union {
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BitField<0, 16, u32> x1;
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BitField<16, 16, u32> y1;
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};
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union {
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BitField<0, 16, u32> x2;
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BitField<16, 16, u32> y2;
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};
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} scissor_test;
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union {
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BitField<0, 10, s32> x;
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BitField<16, 10, s32> y;
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} viewport_corner;
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INSERT_PADDING_WORDS(0x1);
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// TODO: early depth
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INSERT_PADDING_WORDS(0x1);
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INSERT_PADDING_WORDS(0x2);
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enum DepthBuffering : u32 {
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WBuffering = 0,
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ZBuffering = 1,
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};
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BitField<0, 1, DepthBuffering> depthmap_enable;
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INSERT_PADDING_WORDS(0x12);
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};
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static_assert(sizeof(RasterizerRegs) == 0x40 * sizeof(u32),
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"RasterizerRegs struct has incorrect size");
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|
||||
} // namespace Pica
|
|
@ -197,13 +197,16 @@ void RasterizerOpenGL::DrawTriangles() {
|
|||
|
||||
// Sync the viewport
|
||||
// These registers hold half-width and half-height, so must be multiplied by 2
|
||||
GLsizei viewport_width = (GLsizei)Pica::float24::FromRaw(regs.viewport_size_x).ToFloat32() * 2;
|
||||
GLsizei viewport_height = (GLsizei)Pica::float24::FromRaw(regs.viewport_size_y).ToFloat32() * 2;
|
||||
GLsizei viewport_width =
|
||||
(GLsizei)Pica::float24::FromRaw(regs.rasterizer.viewport_size_x).ToFloat32() * 2;
|
||||
GLsizei viewport_height =
|
||||
(GLsizei)Pica::float24::FromRaw(regs.rasterizer.viewport_size_y).ToFloat32() * 2;
|
||||
|
||||
glViewport((GLint)(rect.left + regs.viewport_corner.x * color_surface->res_scale_width),
|
||||
(GLint)(rect.bottom + regs.viewport_corner.y * color_surface->res_scale_height),
|
||||
(GLsizei)(viewport_width * color_surface->res_scale_width),
|
||||
(GLsizei)(viewport_height * color_surface->res_scale_height));
|
||||
glViewport(
|
||||
(GLint)(rect.left + regs.rasterizer.viewport_corner.x * color_surface->res_scale_width),
|
||||
(GLint)(rect.bottom + regs.rasterizer.viewport_corner.y * color_surface->res_scale_height),
|
||||
(GLsizei)(viewport_width * color_surface->res_scale_width),
|
||||
(GLsizei)(viewport_height * color_surface->res_scale_height));
|
||||
|
||||
if (uniform_block_data.data.framebuffer_scale[0] != color_surface->res_scale_width ||
|
||||
uniform_block_data.data.framebuffer_scale[1] != color_surface->res_scale_height) {
|
||||
|
@ -215,16 +218,16 @@ void RasterizerOpenGL::DrawTriangles() {
|
|||
|
||||
// Scissor checks are window-, not viewport-relative, which means that if the cached texture
|
||||
// sub-rect changes, the scissor bounds also need to be updated.
|
||||
GLint scissor_x1 =
|
||||
static_cast<GLint>(rect.left + regs.scissor_test.x1 * color_surface->res_scale_width);
|
||||
GLint scissor_y1 =
|
||||
static_cast<GLint>(rect.bottom + regs.scissor_test.y1 * color_surface->res_scale_height);
|
||||
GLint scissor_x1 = static_cast<GLint>(
|
||||
rect.left + regs.rasterizer.scissor_test.x1 * color_surface->res_scale_width);
|
||||
GLint scissor_y1 = static_cast<GLint>(
|
||||
rect.bottom + regs.rasterizer.scissor_test.y1 * color_surface->res_scale_height);
|
||||
// x2, y2 have +1 added to cover the entire pixel area, otherwise you might get cracks when
|
||||
// scaling or doing multisampling.
|
||||
GLint scissor_x2 =
|
||||
static_cast<GLint>(rect.left + (regs.scissor_test.x2 + 1) * color_surface->res_scale_width);
|
||||
GLint scissor_x2 = static_cast<GLint>(
|
||||
rect.left + (regs.rasterizer.scissor_test.x2 + 1) * color_surface->res_scale_width);
|
||||
GLint scissor_y2 = static_cast<GLint>(
|
||||
rect.bottom + (regs.scissor_test.y2 + 1) * color_surface->res_scale_height);
|
||||
rect.bottom + (regs.rasterizer.scissor_test.y2 + 1) * color_surface->res_scale_height);
|
||||
|
||||
if (uniform_block_data.data.scissor_x1 != scissor_x1 ||
|
||||
uniform_block_data.data.scissor_x2 != scissor_x2 ||
|
||||
|
@ -316,20 +319,20 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
|
|||
|
||||
switch (id) {
|
||||
// Culling
|
||||
case PICA_REG_INDEX(cull_mode):
|
||||
case PICA_REG_INDEX(rasterizer.cull_mode):
|
||||
SyncCullMode();
|
||||
break;
|
||||
|
||||
// Depth modifiers
|
||||
case PICA_REG_INDEX(viewport_depth_range):
|
||||
case PICA_REG_INDEX(rasterizer.viewport_depth_range):
|
||||
SyncDepthScale();
|
||||
break;
|
||||
case PICA_REG_INDEX(viewport_depth_near_plane):
|
||||
case PICA_REG_INDEX(rasterizer.viewport_depth_near_plane):
|
||||
SyncDepthOffset();
|
||||
break;
|
||||
|
||||
// Depth buffering
|
||||
case PICA_REG_INDEX(depthmap_enable):
|
||||
case PICA_REG_INDEX(rasterizer.depthmap_enable):
|
||||
shader_dirty = true;
|
||||
break;
|
||||
|
||||
|
@ -398,7 +401,7 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
|
|||
break;
|
||||
|
||||
// Scissor test
|
||||
case PICA_REG_INDEX(scissor_test.mode):
|
||||
case PICA_REG_INDEX(rasterizer.scissor_test.mode):
|
||||
shader_dirty = true;
|
||||
break;
|
||||
|
||||
|
@ -1110,30 +1113,31 @@ void RasterizerOpenGL::SetShader() {
|
|||
void RasterizerOpenGL::SyncCullMode() {
|
||||
const auto& regs = Pica::g_state.regs;
|
||||
|
||||
switch (regs.cull_mode) {
|
||||
case Pica::Regs::CullMode::KeepAll:
|
||||
switch (regs.rasterizer.cull_mode) {
|
||||
case Pica::RasterizerRegs::CullMode::KeepAll:
|
||||
state.cull.enabled = false;
|
||||
break;
|
||||
|
||||
case Pica::Regs::CullMode::KeepClockWise:
|
||||
case Pica::RasterizerRegs::CullMode::KeepClockWise:
|
||||
state.cull.enabled = true;
|
||||
state.cull.front_face = GL_CW;
|
||||
break;
|
||||
|
||||
case Pica::Regs::CullMode::KeepCounterClockWise:
|
||||
case Pica::RasterizerRegs::CullMode::KeepCounterClockWise:
|
||||
state.cull.enabled = true;
|
||||
state.cull.front_face = GL_CCW;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG_CRITICAL(Render_OpenGL, "Unknown cull mode %d", regs.cull_mode.Value());
|
||||
LOG_CRITICAL(Render_OpenGL, "Unknown cull mode %d", regs.rasterizer.cull_mode.Value());
|
||||
UNIMPLEMENTED();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::SyncDepthScale() {
|
||||
float depth_scale = Pica::float24::FromRaw(Pica::g_state.regs.viewport_depth_range).ToFloat32();
|
||||
float depth_scale =
|
||||
Pica::float24::FromRaw(Pica::g_state.regs.rasterizer.viewport_depth_range).ToFloat32();
|
||||
if (depth_scale != uniform_block_data.data.depth_scale) {
|
||||
uniform_block_data.data.depth_scale = depth_scale;
|
||||
uniform_block_data.dirty = true;
|
||||
|
@ -1142,7 +1146,7 @@ void RasterizerOpenGL::SyncDepthScale() {
|
|||
|
||||
void RasterizerOpenGL::SyncDepthOffset() {
|
||||
float depth_offset =
|
||||
Pica::float24::FromRaw(Pica::g_state.regs.viewport_depth_near_plane).ToFloat32();
|
||||
Pica::float24::FromRaw(Pica::g_state.regs.rasterizer.viewport_depth_near_plane).ToFloat32();
|
||||
if (depth_offset != uniform_block_data.data.depth_offset) {
|
||||
uniform_block_data.data.depth_offset = depth_offset;
|
||||
uniform_block_data.dirty = true;
|
||||
|
|
|
@ -52,9 +52,9 @@ union PicaShaderConfig {
|
|||
|
||||
const auto& regs = Pica::g_state.regs;
|
||||
|
||||
state.scissor_test_mode = regs.scissor_test.mode;
|
||||
state.scissor_test_mode = regs.rasterizer.scissor_test.mode;
|
||||
|
||||
state.depthmap_enable = regs.depthmap_enable;
|
||||
state.depthmap_enable = regs.rasterizer.depthmap_enable;
|
||||
|
||||
state.alpha_test_func = regs.output_merger.alpha_test.enable
|
||||
? regs.output_merger.alpha_test.func.Value()
|
||||
|
@ -172,12 +172,12 @@ union PicaShaderConfig {
|
|||
|
||||
struct State {
|
||||
Pica::Regs::CompareFunc alpha_test_func;
|
||||
Pica::Regs::ScissorMode scissor_test_mode;
|
||||
Pica::RasterizerRegs::ScissorMode scissor_test_mode;
|
||||
Pica::Regs::TextureConfig::TextureType texture0_type;
|
||||
std::array<TevStageConfigRaw, 6> tev_stages;
|
||||
u8 combiner_buffer_input;
|
||||
|
||||
Pica::Regs::DepthBuffering depthmap_enable;
|
||||
Pica::RasterizerRegs::DepthBuffering depthmap_enable;
|
||||
Pica::Regs::FogMode fog_mode;
|
||||
bool fog_flip;
|
||||
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include "video_core/renderer_opengl/gl_shader_util.h"
|
||||
|
||||
using Pica::Regs;
|
||||
using Pica::RasterizerRegs;
|
||||
using TevStageConfig = Regs::TevStageConfig;
|
||||
|
||||
namespace GLShader {
|
||||
|
@ -639,10 +640,10 @@ vec4 secondary_fragment_color = vec4(0.0);
|
|||
}
|
||||
|
||||
// Append the scissor test
|
||||
if (state.scissor_test_mode != Regs::ScissorMode::Disabled) {
|
||||
if (state.scissor_test_mode != RasterizerRegs::ScissorMode::Disabled) {
|
||||
out += "if (";
|
||||
// Negate the condition if we have to keep only the pixels outside the scissor box
|
||||
if (state.scissor_test_mode == Regs::ScissorMode::Include)
|
||||
if (state.scissor_test_mode == RasterizerRegs::ScissorMode::Include)
|
||||
out += "!";
|
||||
out += "(gl_FragCoord.x >= scissor_x1 && "
|
||||
"gl_FragCoord.y >= scissor_y1 && "
|
||||
|
@ -652,7 +653,7 @@ vec4 secondary_fragment_color = vec4(0.0);
|
|||
|
||||
out += "float z_over_w = 1.0 - gl_FragCoord.z * 2.0;\n";
|
||||
out += "float depth = z_over_w * depth_scale + depth_offset;\n";
|
||||
if (state.depthmap_enable == Pica::Regs::DepthBuffering::WBuffering) {
|
||||
if (state.depthmap_enable == Pica::RasterizerRegs::DepthBuffering::WBuffering) {
|
||||
out += "depth /= gl_FragCoord.w;\n";
|
||||
}
|
||||
|
||||
|
|
|
@ -20,7 +20,7 @@ namespace Pica {
|
|||
|
||||
namespace Shader {
|
||||
|
||||
OutputVertex OutputVertex::FromAttributeBuffer(const Regs& regs, AttributeBuffer& input) {
|
||||
OutputVertex OutputVertex::FromAttributeBuffer(const RasterizerRegs& regs, AttributeBuffer& input) {
|
||||
// Setup output data
|
||||
union {
|
||||
OutputVertex ret{};
|
||||
|
@ -33,16 +33,16 @@ OutputVertex OutputVertex::FromAttributeBuffer(const Regs& regs, AttributeBuffer
|
|||
for (unsigned int i = 0; i < num_attributes; ++i) {
|
||||
const auto& output_register_map = regs.vs_output_attributes[i];
|
||||
|
||||
Regs::VSOutputAttributes::Semantic semantics[4] = {
|
||||
RasterizerRegs::VSOutputAttributes::Semantic semantics[4] = {
|
||||
output_register_map.map_x, output_register_map.map_y, output_register_map.map_z,
|
||||
output_register_map.map_w};
|
||||
|
||||
for (unsigned comp = 0; comp < 4; ++comp) {
|
||||
Regs::VSOutputAttributes::Semantic semantic = semantics[comp];
|
||||
RasterizerRegs::VSOutputAttributes::Semantic semantic = semantics[comp];
|
||||
float24* out = &vertex_slots[semantic];
|
||||
if (semantic < vertex_slots.size()) {
|
||||
*out = input.attr[i][comp];
|
||||
} else if (semantic != Regs::VSOutputAttributes::INVALID) {
|
||||
} else if (semantic != RasterizerRegs::VSOutputAttributes::INVALID) {
|
||||
LOG_ERROR(HW_GPU, "Invalid/unknown semantic id: %u", (unsigned int)semantic);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -39,19 +39,19 @@ struct OutputVertex {
|
|||
INSERT_PADDING_WORDS(1);
|
||||
Math::Vec2<float24> tc2;
|
||||
|
||||
static OutputVertex FromAttributeBuffer(const Regs& regs, AttributeBuffer& output);
|
||||
static OutputVertex FromAttributeBuffer(const RasterizerRegs& regs, AttributeBuffer& output);
|
||||
};
|
||||
#define ASSERT_POS(var, pos) \
|
||||
static_assert(offsetof(OutputVertex, var) == pos * sizeof(float24), "Semantic at wrong " \
|
||||
"offset.")
|
||||
ASSERT_POS(pos, Regs::VSOutputAttributes::POSITION_X);
|
||||
ASSERT_POS(quat, Regs::VSOutputAttributes::QUATERNION_X);
|
||||
ASSERT_POS(color, Regs::VSOutputAttributes::COLOR_R);
|
||||
ASSERT_POS(tc0, Regs::VSOutputAttributes::TEXCOORD0_U);
|
||||
ASSERT_POS(tc1, Regs::VSOutputAttributes::TEXCOORD1_U);
|
||||
ASSERT_POS(tc0_w, Regs::VSOutputAttributes::TEXCOORD0_W);
|
||||
ASSERT_POS(view, Regs::VSOutputAttributes::VIEW_X);
|
||||
ASSERT_POS(tc2, Regs::VSOutputAttributes::TEXCOORD2_U);
|
||||
ASSERT_POS(pos, RasterizerRegs::VSOutputAttributes::POSITION_X);
|
||||
ASSERT_POS(quat, RasterizerRegs::VSOutputAttributes::QUATERNION_X);
|
||||
ASSERT_POS(color, RasterizerRegs::VSOutputAttributes::COLOR_R);
|
||||
ASSERT_POS(tc0, RasterizerRegs::VSOutputAttributes::TEXCOORD0_U);
|
||||
ASSERT_POS(tc1, RasterizerRegs::VSOutputAttributes::TEXCOORD1_U);
|
||||
ASSERT_POS(tc0_w, RasterizerRegs::VSOutputAttributes::TEXCOORD0_W);
|
||||
ASSERT_POS(view, RasterizerRegs::VSOutputAttributes::VIEW_X);
|
||||
ASSERT_POS(tc2, RasterizerRegs::VSOutputAttributes::TEXCOORD2_U);
|
||||
#undef ASSERT_POS
|
||||
static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
|
||||
static_assert(sizeof(OutputVertex) == 24 * sizeof(float), "OutputVertex has invalid size");
|
||||
|
|
Reference in New Issue