Removed common/atomic, instead using std::atomic
This commit is contained in:
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c0e48432cd
commit
4795a64fc8
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@ -23,9 +23,6 @@ set(SRCS
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)
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set(HEADERS
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atomic.h
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atomic_gcc.h
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atomic_win32.h
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bit_field.h
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break_points.h
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chunk_file.h
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@ -1,16 +0,0 @@
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// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#ifdef _WIN32
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#include "common/atomic_win32.h"
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#else
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// GCC-compatible compiler assumed!
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#include "common/atomic_gcc.h"
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#endif
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@ -1,110 +0,0 @@
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// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common.h"
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value) {
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__sync_add_and_fetch(&target, value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value) {
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__sync_and_and_fetch(&target, value);
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}
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inline void AtomicDecrement(volatile u32& target) {
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__sync_add_and_fetch(&target, -1);
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}
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inline void AtomicIncrement(volatile u32& target) {
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__sync_add_and_fetch(&target, 1);
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}
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inline u32 AtomicLoad(volatile u32& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline u32 AtomicLoadAcquire(volatile u32& src) {
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//keep the compiler from caching any memory references
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u32 result = src; // 32-bit reads are always atomic.
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//__sync_synchronize(); // TODO: May not be necessary.
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// Compiler instruction only. x86 loads always have acquire semantics.
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__asm__ __volatile__ ( "":::"memory" );
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return result;
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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__sync_or_and_fetch(&target, value);
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}
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inline void AtomicStore(volatile u32& dest, u32 value) {
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dest = value; // 32-bit writes are always atomic.
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}
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inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
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__sync_lock_test_and_set(&dest, value); // TODO: Wrong! This function is has acquire semantics.
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}
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}
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// Old code kept here for reference in case we need the parts with __asm__ __volatile__.
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#if 0
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LONG SyncInterlockedIncrement(LONG *Dest)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_add_and_fetch(Dest, 1);
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (1), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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LONG SyncInterlockedExchangeAdd(LONG *Dest, LONG Val)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_add_and_fetch(Dest, Val);
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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LONG SyncInterlockedExchange(LONG *Dest, LONG Val)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_lock_test_and_set(Dest, Val);
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#else
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register int result;
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__asm__ __volatile__("lock; xchg %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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#endif
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@ -1,69 +0,0 @@
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// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common.h"
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#include <intrin.h>
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#include <Windows.h>
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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//
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// NOTE: Acquire and Release are not differentiated right now. They perform a
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// full memory barrier instead of a "one-way" memory barrier. The newest
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// Windows SDK has Acquire and Release versions of some Interlocked* functions.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value) {
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InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value) {
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_InterlockedAnd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicIncrement(volatile u32& target) {
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InterlockedIncrement((volatile LONG*)&target);
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}
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inline void AtomicDecrement(volatile u32& target) {
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InterlockedDecrement((volatile LONG*)&target);
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}
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inline u32 AtomicLoad(volatile u32& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline u32 AtomicLoadAcquire(volatile u32& src) {
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u32 result = src; // 32-bit reads are always atomic.
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_ReadBarrier(); // Compiler instruction only. x86 loads always have acquire semantics.
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return result;
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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_InterlockedOr((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicStore(volatile u32& dest, u32 value) {
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dest = value; // 32-bit writes are always atomic.
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}
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inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
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_WriteBarrier(); // Compiler instruction only. x86 stores always have release semantics.
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dest = value; // 32-bit writes are always atomic.
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}
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}
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@ -4,10 +4,10 @@
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#include <vector>
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#include <cstdio>
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#include <atomic>
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#include "common/msg_handler.h"
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#include "common/std_mutex.h"
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#include "common/atomic.h"
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#include "common/chunk_file.h"
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#include "core/core_timing.h"
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@ -54,7 +54,7 @@ Event *eventPool = 0;
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Event *eventTsPool = 0;
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int allocatedTsEvents = 0;
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// Optimization to skip MoveEvents when possible.
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volatile u32 hasTsEvents = false;
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std::atomic<u32> hasTsEvents;
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// Downcount has been moved to currentMIPS, to save a couple of clocks in every ARM JIT block
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// as we can already reach that structure through a register.
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@ -202,7 +202,7 @@ void ScheduleEvent_Threadsafe(s64 cyclesIntoFuture, int event_type, u64 userdata
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tsLast->next = ne;
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tsLast = ne;
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Common::AtomicStoreRelease(hasTsEvents, 1);
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hasTsEvents.store(1, std::memory_order_release);
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}
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// Same as ScheduleEvent_Threadsafe(0, ...) EXCEPT if we are already on the CPU thread
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@ -484,7 +484,7 @@ void ProcessFifoWaitEvents()
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void MoveEvents()
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{
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Common::AtomicStoreRelease(hasTsEvents, 0);
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hasTsEvents.store(0, std::memory_order_release);
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std::lock_guard<std::recursive_mutex> lk(externalEventSection);
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// Move events from async queue into main queue
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