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armemu: Implement UMAAL

This commit is contained in:
Lioncash 2014-12-17 12:13:35 -05:00
parent fdb4ef5210
commit 5820dba6b7
1 changed files with 25 additions and 3 deletions
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26
src/core/arm/interpreter/armemu.cpp
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@ -1357,6 +1357,12 @@ mainswitch:
break; break;
case 0x04: /* SUB reg */ case 0x04: /* SUB reg */
// Signifies UMAAL
if (state->is_v6 && BITS(4, 7) == 0x09) {
if (handle_v6_insn(state, instr))
break;
}
#ifdef MODET #ifdef MODET
if (BITS (4, 7) == 0xB) { if (BITS (4, 7) == 0xB) {
/* STRH immediate offset, no write-back, down, post indexed. */ /* STRH immediate offset, no write-back, down, post indexed. */
@ -5677,8 +5683,24 @@ L_stm_s_takeabort:
case 0x03: case 0x03:
printf ("Unhandled v6 insn: ldr\n"); printf ("Unhandled v6 insn: ldr\n");
break; break;
case 0x04: case 0x04: // UMAAL
printf ("Unhandled v6 insn: umaal\n"); {
const u8 rm_idx = BITS(8, 11);
const u8 rn_idx = BITS(0, 3);
const u8 rd_lo_idx = BITS(12, 15);
const u8 rd_hi_idx = BITS(16, 19);
const u32 rm_val = state->Reg[rm_idx];
const u32 rn_val = state->Reg[rn_idx];
const u32 rd_lo_val = state->Reg[rd_lo_idx];
const u32 rd_hi_val = state->Reg[rd_hi_idx];
const u64 result = (rn_val * rm_val) + rd_lo_val + rd_hi_val;
state->Reg[rd_lo_idx] = (result & 0xFFFFFFFF);
state->Reg[rd_hi_idx] = ((result >> 32) & 0xFFFFFFFF);
return 1;
}
break; break;
case 0x06: case 0x06:
printf ("Unhandled v6 insn: mls/str\n"); printf ("Unhandled v6 insn: mls/str\n");