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armemu: Simplify SSAT/SSAT16/SXTB/SXTAB

This commit is contained in:
Lioncash 2014-12-28 12:19:31 -05:00
parent 9f5b53f9ff
commit 6ce2a38ec4
1 changed files with 46 additions and 69 deletions
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113
src/core/arm/interpreter/armemu.cpp
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@ -6272,84 +6272,61 @@ L_stm_s_takeabort:
return 1; return 1;
} }
} }
printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n");
break; break;
case 0x6a: {
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) { case 0x6a: // SSAT, SSAT16, SXTB, and SXTAB
case 0x07: {
ror = 0; const u8 op2 = BITS(5, 7);
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0x01: // SSAT16
case 0xf3: if (op2 == 0x01) {
//ichfly const u8 rd_idx = BITS(12, 15);
//SSAT16 const u8 rn_idx = BITS(0, 3);
{ const u8 num_bits = BITS(16, 19) + 1;
const u8 rd_idx = BITS(12, 15); const s16 min = -(0x8000 >> (16 - num_bits));
const u8 rn_idx = BITS(0, 3); const s16 max = (0x7FFF >> (16 - num_bits));
const u8 num_bits = BITS(16, 19) + 1; s16 rn_lo = (state->Reg[rn_idx]);
const s16 min = -(0x8000 >> (16 - num_bits)); s16 rn_hi = (state->Reg[rn_idx] >> 16);
const s16 max = (0x7FFF >> (16 - num_bits));
s16 rn_lo = (state->Reg[rn_idx]);
s16 rn_hi = (state->Reg[rn_idx] >> 16);
if (rn_lo > max) { if (rn_lo > max) {
rn_lo = max; rn_lo = max;
SETQ; SETQ;
} else if (rn_lo < min) { } else if (rn_lo < min) {
rn_lo = min; rn_lo = min;
SETQ; SETQ;
}
if (rn_hi > max) {
rn_hi = max;
SETQ;
} else if (rn_hi < min) {
rn_hi = min;
SETQ;
}
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
return 1;
} }
default: if (rn_hi > max) {
break; rn_hi = max;
} SETQ;
} else if (rn_hi < min) {
if (ror == -1) { rn_hi = min;
if (BITS(4, 6) == 0x7) { SETQ;
printf("Unhandled v6 insn: ssat\n");
return 0;
} }
break;
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
return 1;
} }
else if (op2 == 0x03) {
const u8 rotation = BITS(10, 11) * 8;
u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
if (rm & 0x80)
rm |= 0xffffff00;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); // SXTB, otherwise SXTAB
if (Rm & 0x80) if (BITS(16, 19) == 0xf)
Rm |= 0xffffff00; state->Reg[BITS(12, 15)] = rm;
else
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
if (BITS(16, 19) == 0xf) return 1;
/* SXTB */ }
state->Reg[BITS(12, 15)] = Rm; else {
else printf("Unimplemented op: SSAT");
/* SXTAB */ }
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
return 1;
} }
break;
case 0x6b: // REV, REV16, SXTH, and SXTAH case 0x6b: // REV, REV16, SXTH, and SXTAH
{ {