Merge pull request #652 from neobrain/shader_output_fix
Pica/VertexShader: Fix a bug caused due to incorrect assumptions of consecutive output register tables.
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commit
c1f5cb7dd5
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@ -72,7 +72,7 @@ struct VertexShaderState {
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u32* program_counter;
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const float24* input_register_table[16];
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float24* output_register_table[7*4];
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Math::Vec4<float24> output_registers[16];
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Math::Vec4<float24> temporary_registers[16];
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bool conditional_code[2];
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@ -198,8 +198,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.common.dest.Value() < 0x08) ? state.output_register_table[4*instr.common.dest.Value().GetIndex()]
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: (instr.common.dest.Value() < 0x10) ? dummy_vec4_float24
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float24* dest = (instr.common.dest.Value() < 0x10) ? &state.output_registers[instr.common.dest.Value().GetIndex()][0]
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: (instr.common.dest.Value() < 0x20) ? &state.temporary_registers[instr.common.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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@ -409,8 +408,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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src3[3] = src3[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.mad.dest.Value() < 0x08) ? state.output_register_table[4*instr.mad.dest.Value().GetIndex()]
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: (instr.mad.dest.Value() < 0x10) ? dummy_vec4_float24
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float24* dest = (instr.mad.dest.Value() < 0x10) ? &state.output_registers[instr.mad.dest.Value().GetIndex()][0]
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: (instr.mad.dest.Value() < 0x20) ? &state.temporary_registers[instr.mad.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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@ -587,12 +585,18 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes) {
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if(num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
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if(num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
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// Setup output register table
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OutputVertex ret;
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// Zero output so that attributes which aren't output won't have denormals in them, which will
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// slow us down later.
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memset(&ret, 0, sizeof(ret));
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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ProcessShaderCode(state);
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DebugUtils::DumpShader(shader_memory.data(), state.debug.max_offset, swizzle_data.data(),
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state.debug.max_opdesc_id, registers.vs_main_offset,
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registers.vs_output_attributes);
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = registers.vs_output_attributes[i];
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@ -601,18 +605,18 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes) {
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output_register_map.map_z, output_register_map.map_w
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};
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for (int comp = 0; comp < 4; ++comp)
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state.output_register_table[4*i+comp] = ((float24*)&ret) + semantics[comp];
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for (int comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.output_registers[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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}
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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ProcessShaderCode(state);
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DebugUtils::DumpShader(shader_memory.data(), state.debug.max_offset, swizzle_data.data(),
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state.debug.max_opdesc_id, registers.vs_main_offset,
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registers.vs_output_attributes);
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LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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