shader: Fix address register offset behavior in x64 Jit (#6942)
* shader: Fix address register offset behavior in x64 Jit * shader: Remove redundant jump * tests: Add address register tests * shader: Remove additional pre-multiplications by 16 * tests: Add catch-stringifier for vec4f * tests: Format
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@ -28,6 +28,15 @@ static constexpr Common::Vec4f vec4_nan = Common::Vec4f::AssignToAll(NAN);
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static constexpr Common::Vec4f vec4_one = Common::Vec4f::AssignToAll(1.0f);
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static constexpr Common::Vec4f vec4_zero = Common::Vec4f::AssignToAll(0.0f);
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namespace Catch {
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template <>
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struct StringMaker<Common::Vec4f> {
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static std::string convert(Common::Vec4f value) {
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return fmt::format("({}, {}, {}, {})", value.r(), value.g(), value.b(), value.a());
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}
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};
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} // namespace Catch
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static std::unique_ptr<Pica::Shader::ShaderSetup> CompileShaderSetup(
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std::initializer_list<nihstro::InlineAsm> code) {
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const auto shbin = nihstro::InlineAsm::CompileToRawBinary(code);
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@ -385,6 +394,56 @@ TEST_CASE("RSQ", "[video_core][shader][shader_jit]") {
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REQUIRE(shader.Run({0.0625f}).x == Catch::Approx(4.0f).margin(0.004f));
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}
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TEST_CASE("Address Register Offset", "[video_core][shader][shader_jit]") {
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const auto sh_input = SourceRegister::MakeInput(0);
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const auto sh_c40 = SourceRegister::MakeFloat(40);
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const auto sh_output = DestRegister::MakeOutput(0);
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auto shader = ShaderTest({
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// mova a0.x, sh_input.x
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{OpCode::Id::MOVA, DestRegister{}, "x", sh_input, "x", SourceRegister{}, "",
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nihstro::InlineAsm::RelativeAddress::A1},
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// mov sh_output.xyzw, c40[a0.x].xyzw
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{OpCode::Id::MOV, sh_output, "xyzw", sh_c40, "xyzw", SourceRegister{}, "",
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nihstro::InlineAsm::RelativeAddress::A1},
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{OpCode::Id::END},
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});
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// Prepare shader uniforms
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const bool inverted = true;
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std::array<Common::Vec4f, 96> f_uniforms;
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for (u32 i = 0; i < 0x80; i++) {
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if (i >= 0x00 && i < 0x60) {
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const u32 base = inverted ? (0x60 - i) : i;
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const auto color = (base * 2.f) / 255.0f;
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const auto color_f24 = Pica::f24::FromFloat32(color);
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shader.shader_setup->uniforms.f[i] = {color_f24, color_f24, color_f24,
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Pica::f24::One()};
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f_uniforms[i] = {color, color, color, 1.f};
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} else if (i >= 0x60 && i < 0x70) {
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const u8 color = static_cast<u8>((i - 0x60) * 0x10);
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shader.shader_setup->uniforms.i[i - 0x60] = {color, color, color, 255};
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} else if (i >= 0x70 && i < 0x80) {
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shader.shader_setup->uniforms.b[i - 0x70] = i >= 0x78;
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}
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}
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REQUIRE(shader.Run(0.f) == f_uniforms[40]);
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REQUIRE(shader.Run(13.f) == f_uniforms[53]);
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REQUIRE(shader.Run(50.f) == f_uniforms[90]);
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REQUIRE(shader.Run(60.f) == vec4_one);
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REQUIRE(shader.Run(74.f) == vec4_one);
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REQUIRE(shader.Run(87.f) == vec4_one);
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REQUIRE(shader.Run(88.f) == f_uniforms[0]);
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REQUIRE(shader.Run(128.f) == f_uniforms[40]);
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REQUIRE(shader.Run(-40.f) == f_uniforms[0]);
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REQUIRE(shader.Run(-42.f) == vec4_one);
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REQUIRE(shader.Run(-70.f) == vec4_one);
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REQUIRE(shader.Run(-73.f) == f_uniforms[95]);
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REQUIRE(shader.Run(-127.f) == f_uniforms[41]);
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REQUIRE(shader.Run(-129.f) == f_uniforms[40]);
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}
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// TODO: Requires fix from https://github.com/neobrain/nihstro/issues/68
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// TEST_CASE("MAD", "[video_core][shader][shader_jit]") {
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// const auto sh_input1 = SourceRegister::MakeInput(0);
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@ -232,21 +232,45 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
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address_register_index = instr.common.address_register_index;
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}
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if (src_num == offset_src && address_register_index != 0) {
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform && src_num == offset_src &&
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address_register_index != 0) {
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Xbyak::Reg64 address_reg;
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switch (address_register_index) {
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case 1: // address offset 1
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movaps(dest, xword[src_ptr + ADDROFFS_REG_0 + src_offset_disp]);
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case 1:
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address_reg = ADDROFFS_REG_0;
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break;
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case 2: // address offset 2
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movaps(dest, xword[src_ptr + ADDROFFS_REG_1 + src_offset_disp]);
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case 2:
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address_reg = ADDROFFS_REG_1;
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break;
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case 3: // address offset 3
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movaps(dest, xword[src_ptr + LOOPCOUNT_REG.cvt64() + src_offset_disp]);
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case 3:
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address_reg = LOOPCOUNT_REG.cvt64();
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break;
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default:
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UNREACHABLE();
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break;
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}
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// s32 offset = address_reg >= -128 && address_reg <= 127 ? address_reg : 0;
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// u32 index = (src_reg.GetIndex() + offset) & 0x7f;
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// First we add 128 to address_reg so the first comparison is turned to
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// address_reg >= 0 && address_reg < 256 which can be performed with
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// a single unsigned comparison (cmovb)
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lea(eax, ptr[address_reg + 128]);
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mov(ebx, src_reg.GetIndex());
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mov(ecx, address_reg.cvt32());
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add(ecx, ebx);
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cmp(eax, 256);
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cmovb(ebx, ecx);
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and_(ebx, 0x7f);
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// index > 95 ? vec4(1.0) : uniforms.f[index];
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movaps(dest, ONE);
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cmp(ebx, 95);
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Label load_end;
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jg(load_end);
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shl(rbx, 4);
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movaps(dest, xword[src_ptr + rbx]);
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L(load_end);
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} else {
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// Load the source
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movaps(dest, xword[src_ptr + src_offset_disp]);
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@ -590,24 +614,14 @@ void JitShader::Compile_MOVA(Instruction instr) {
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// Move and sign-extend high 32 bits
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shr(rax, 32);
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movsxd(ADDROFFS_REG_1, eax);
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// Multiply by 16 to be used as an offset later
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shl(ADDROFFS_REG_0, 4);
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shl(ADDROFFS_REG_1, 4);
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} else {
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if (swiz.DestComponentEnabled(0)) {
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// Move and sign-extend low 32 bits
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movsxd(ADDROFFS_REG_0, eax);
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// Multiply by 16 to be used as an offset later
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shl(ADDROFFS_REG_0, 4);
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} else if (swiz.DestComponentEnabled(1)) {
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// Move and sign-extend high 32 bits
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shr(rax, 32);
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movsxd(ADDROFFS_REG_1, eax);
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// Multiply by 16 to be used as an offset later
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shl(ADDROFFS_REG_1, 4);
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}
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}
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}
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@ -659,9 +673,6 @@ void JitShader::Compile_END(Instruction instr) {
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mov(byte[STATE + offsetof(UnitState, conditional_code[1])], COND1.cvt8());
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// Save address/loop registers
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sar(ADDROFFS_REG_0, 4);
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sar(ADDROFFS_REG_1, 4);
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sar(LOOPCOUNT_REG, 4);
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mov(dword[STATE + offsetof(UnitState, address_registers[0])], ADDROFFS_REG_0.cvt32());
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mov(dword[STATE + offsetof(UnitState, address_registers[1])], ADDROFFS_REG_1.cvt32());
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mov(dword[STATE + offsetof(UnitState, address_registers[2])], LOOPCOUNT_REG);
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@ -813,11 +824,11 @@ void JitShader::Compile_LOOP(Instruction instr) {
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std::size_t offset = Uniforms::GetIntUniformOffset(instr.flow_control.int_uniform_id);
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mov(LOOPCOUNT, dword[UNIFORMS + offset]);
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mov(LOOPCOUNT_REG, LOOPCOUNT);
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shr(LOOPCOUNT_REG, 4);
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and_(LOOPCOUNT_REG, 0xFF0); // Y-component is the start
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shr(LOOPCOUNT_REG, 8);
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and_(LOOPCOUNT_REG, 0xFF); // Y-component is the start
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mov(LOOPINC, LOOPCOUNT);
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shr(LOOPINC, 12);
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and_(LOOPINC, 0xFF0); // Z-component is the incrementer
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shr(LOOPINC, 16);
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and_(LOOPINC, 0xFF); // Z-component is the incrementer
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movzx(LOOPCOUNT, LOOPCOUNT.cvt8()); // X-component is iteration count
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add(LOOPCOUNT, 1); // Iteration count is X-component + 1
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@ -993,9 +1004,6 @@ void JitShader::Compile(const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_
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movsxd(ADDROFFS_REG_0, dword[STATE + offsetof(UnitState, address_registers[0])]);
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movsxd(ADDROFFS_REG_1, dword[STATE + offsetof(UnitState, address_registers[1])]);
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mov(LOOPCOUNT_REG, dword[STATE + offsetof(UnitState, address_registers[2])]);
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shl(ADDROFFS_REG_0, 4);
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shl(ADDROFFS_REG_1, 4);
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shl(LOOPCOUNT_REG, 4);
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// Load conditional code
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mov(COND0, byte[STATE + offsetof(UnitState, conditional_code[0])]);
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