dyncom: Fix overflow flag setting for ADD/RSB/RSC/SUB/SBC
Also cleans up CMN, and CMP.
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9c2c89b7e1
commit
3ace75a49f
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@ -4034,14 +4034,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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ADD_INST:
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{
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add_inst *inst_cream = (add_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 2 * GET_INST_SIZE(cpu);
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}
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rop = SHIFTER_OPERAND;
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RD = dst = lop + rop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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add_inst* const inst_cream = (add_inst*)inst_base->component;
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u32 rn_val = RN;
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if (inst_cream->Rn == 15)
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rn_val += 2 * GET_INST_SIZE(cpu);
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bool carry;
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bool overflow;
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RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -4049,10 +4052,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG(dst, lop, rop);
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UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(add_inst));
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@ -5459,11 +5462,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SBC_INST:
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{
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sbc_inst *inst_cream = (sbc_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = SHIFTER_OPERAND + !cpu->CFlag;
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rop = RN;
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RD = dst = rop - lop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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sbc_inst* const inst_cream = (sbc_inst*)inst_base->component;
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bool carry;
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bool overflow;
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RD = AddWithCarry(RN, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -5471,15 +5476,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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if(rop >= !cpu->CFlag)
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UPDATE_CFLAG_NOT_BORROW_FROM(rop - !cpu->CFlag, SHIFTER_OPERAND);
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else
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UPDATE_CFLAG_NOT_BORROW_FROM(rop, !cpu->CFlag);
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UPDATE_VFLAG_OVERFLOW_FROM(dst, rop, lop);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(sbc_inst));
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@ -6257,14 +6257,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SUB_INST:
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{
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sub_inst *inst_cream = (sub_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 8;
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}
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rop = SHIFTER_OPERAND;
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RD = dst = lop - rop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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sub_inst* const inst_cream = (sub_inst*)inst_base->component;
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u32 rn_val = RN;
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if (inst_cream->Rn == 15)
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rn_val += 8;
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bool carry;
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bool overflow;
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RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -6272,10 +6275,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
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UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(sub_inst));
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