citra-emu
/
citra
Archived
1
0
Fork 0
Code

vfp_helper: Convert some flags to enums. Throw out more duplicated FPSCR stuff

This commit is contained in:
Lioncash 2015-02-09 09:51:15 -05:00
parent d832c48864
commit ca7babe062
4 changed files with 142 additions and 181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/core/arm/skyeye_common/vfp/vfp.cpp
View File

@ -773,8 +773,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
* Comparison instructions always return at least one of * Comparison instructions always return at least one of
* these flags set. * these flags set.
*/ */
if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) if (exceptions & (FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG))
fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); fpscr &= ~(FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG);
fpscr |= exceptions; fpscr |= exceptions;

225
src/core/arm/skyeye_common/vfp/vfp_helper.h
View File

@ -45,46 +45,40 @@
#define do_div(n, base) {n/=base;} #define do_div(n, base) {n/=base;}
/* From vfpinstr.h */ enum : u32 {
FOP_MASK = 0x00b00040,
#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000) FOP_FMAC = 0x00000000,
#define INST_CPRT(inst) ((inst) & (1 << 4)) FOP_FNMAC = 0x00000040,
#define INST_CPRT_L(inst) ((inst) & (1 << 20)) FOP_FMSC = 0x00100000,
#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12) FOP_FNMSC = 0x00100040,
#define INST_CPRT_OP(inst) (((inst) >> 21) & 7) FOP_FMUL = 0x00200000,
#define INST_CPNUM(inst) ((inst) & 0xf00) FOP_FNMUL = 0x00200040,
#define CPNUM(cp) ((cp) << 8) FOP_FADD = 0x00300000,
FOP_FSUB = 0x00300040,
#define FOP_MASK (0x00b00040) FOP_FDIV = 0x00800000,
#define FOP_FMAC (0x00000000) FOP_EXT = 0x00b00040
#define FOP_FNMAC (0x00000040) };
#define FOP_FMSC (0x00100000)
#define FOP_FNMSC (0x00100040)
#define FOP_FMUL (0x00200000)
#define FOP_FNMUL (0x00200040)
#define FOP_FADD (0x00300000)
#define FOP_FSUB (0x00300040)
#define FOP_FDIV (0x00800000)
#define FOP_EXT (0x00b00040)
#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
#define FEXT_MASK (0x000f0080) enum : u32 {
#define FEXT_FCPY (0x00000000) FEXT_MASK = 0x000f0080,
#define FEXT_FABS (0x00000080) FEXT_FCPY = 0x00000000,
#define FEXT_FNEG (0x00010000) FEXT_FABS = 0x00000080,
#define FEXT_FSQRT (0x00010080) FEXT_FNEG = 0x00010000,
#define FEXT_FCMP (0x00040000) FEXT_FSQRT = 0x00010080,
#define FEXT_FCMPE (0x00040080) FEXT_FCMP = 0x00040000,
#define FEXT_FCMPZ (0x00050000) FEXT_FCMPE = 0x00040080,
#define FEXT_FCMPEZ (0x00050080) FEXT_FCMPZ = 0x00050000,
#define FEXT_FCVT (0x00070080) FEXT_FCMPEZ = 0x00050080,
#define FEXT_FUITO (0x00080000) FEXT_FCVT = 0x00070080,
#define FEXT_FSITO (0x00080080) FEXT_FUITO = 0x00080000,
#define FEXT_FTOUI (0x000c0000) FEXT_FSITO = 0x00080080,
#define FEXT_FTOUIZ (0x000c0080) FEXT_FTOUI = 0x000c0000,
#define FEXT_FTOSI (0x000d0000) FEXT_FTOUIZ = 0x000c0080,
#define FEXT_FTOSIZ (0x000d0080) FEXT_FTOSI = 0x000d0000,
FEXT_FTOSIZ = 0x000d0080
};
#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
@ -97,11 +91,6 @@
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
#define FPSCR_N (1 << 31)
#define FPSCR_Z (1 << 30)
#define FPSCR_C (1 << 29)
#define FPSCR_V (1 << 28)
static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
{ {
if (shift) { if (shift) {
@ -225,51 +214,39 @@ static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
return z; return z;
} }
/* // Operations on unpacked elements
* Operations on unpacked elements
*/
#define vfp_sign_negate(sign) (sign ^ 0x8000) #define vfp_sign_negate(sign) (sign ^ 0x8000)
/* // Single-precision
* Single-precision
*/
struct vfp_single { struct vfp_single {
s16 exponent; s16 exponent;
u16 sign; u16 sign;
u32 significand; u32 significand;
}; };
/* // VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
* VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa // VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
* VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent // VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand
* VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand // which are not propagated to the float upon packing.
* which are not propagated to the float upon packing.
*/
#define VFP_SINGLE_MANTISSA_BITS (23) #define VFP_SINGLE_MANTISSA_BITS (23)
#define VFP_SINGLE_EXPONENT_BITS (8) #define VFP_SINGLE_EXPONENT_BITS (8)
#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2) #define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2)
#define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1) #define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1)
/* // The bit in an unpacked float which indicates that it is a quiet NaN
* The bit in an unpacked float which indicates that it is a quiet NaN
*/
#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS)) #define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS))
/* // Operations on packed single-precision numbers
* Operations on packed single-precision numbers
*/
#define vfp_single_packed_sign(v) ((v) & 0x80000000) #define vfp_single_packed_sign(v) ((v) & 0x80000000)
#define vfp_single_packed_negate(v) ((v) ^ 0x80000000) #define vfp_single_packed_negate(v) ((v) ^ 0x80000000)
#define vfp_single_packed_abs(v) ((v) & ~0x80000000) #define vfp_single_packed_abs(v) ((v) & ~0x80000000)
#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1)) #define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
#define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1)) #define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
/* // Unpack a single-precision float. Note that this returns the magnitude
* Unpack a single-precision float. Note that this returns the magnitude // of the single-precision float mantissa with the 1. if necessary,
* of the single-precision float mantissa with the 1. if necessary, // aligned to bit 30.
* aligned to bit 30. static inline void vfp_single_unpack(vfp_single* s, s32 val)
*/
static inline void vfp_single_unpack(struct vfp_single *s, s32 val)
{ {
u32 significand; u32 significand;
@ -283,11 +260,9 @@ static inline void vfp_single_unpack(struct vfp_single *s, s32 val)
s->significand = significand; s->significand = significand;
} }
/* // Re-pack a single-precision float. This assumes that the float is
* Re-pack a single-precision float. This assumes that the float is // already normalised such that the MSB is bit 30, _not_ bit 31.
* already normalised such that the MSB is bit 30, _not_ bit 31. static inline s32 vfp_single_pack(vfp_single* s)
*/
static inline s32 vfp_single_pack(struct vfp_single *s)
{ {
u32 val = (s->sign << 16) + u32 val = (s->sign << 16) +
(s->exponent << VFP_SINGLE_MANTISSA_BITS) + (s->exponent << VFP_SINGLE_MANTISSA_BITS) +
@ -295,17 +270,19 @@ static inline s32 vfp_single_pack(struct vfp_single *s)
return (s32)val; return (s32)val;
} }
#define VFP_NUMBER (1<<0) enum : u32 {
#define VFP_ZERO (1<<1) VFP_NUMBER = (1 << 0),
#define VFP_DENORMAL (1<<2) VFP_ZERO = (1 << 1),
#define VFP_INFINITY (1<<3) VFP_DENORMAL = (1 << 2),
#define VFP_NAN (1<<4) VFP_INFINITY = (1 << 3),
#define VFP_NAN_SIGNAL (1<<5) VFP_NAN = (1 << 4),
VFP_NAN_SIGNAL = (1 << 5),
#define VFP_QNAN (VFP_NAN) VFP_QNAN = (VFP_NAN),
#define VFP_SNAN (VFP_NAN|VFP_NAN_SIGNAL) VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
};
static inline int vfp_single_type(struct vfp_single *s) static inline int vfp_single_type(vfp_single* s)
{ {
int type = VFP_NUMBER; int type = VFP_NUMBER;
if (s->exponent == 255) { if (s->exponent == 255) {
@ -325,22 +302,18 @@ static inline int vfp_single_type(struct vfp_single *s)
} }
u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions, const char *func); u32 vfp_single_normaliseround(ARMul_State* state, int sd, vfp_single* vs, u32 fpscr, u32 exceptions, const char* func);
/* // Double-precision
* Double-precision
*/
struct vfp_double { struct vfp_double {
s16 exponent; s16 exponent;
u16 sign; u16 sign;
u64 significand; u64 significand;
}; };
/* // VFP_REG_ZERO is a special register number for vfp_get_double
* VFP_REG_ZERO is a special register number for vfp_get_double // which returns (double)0.0. This is useful for the compare with
* which returns (double)0.0. This is useful for the compare with // zero instructions.
* zero instructions.
*/
#ifdef CONFIG_VFPv3 #ifdef CONFIG_VFPv3
#define VFP_REG_ZERO 32 #define VFP_REG_ZERO 32
#else #else
@ -352,26 +325,20 @@ struct vfp_double {
#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2) #define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2)
#define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1) #define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1)
/* // The bit in an unpacked double which indicates that it is a quiet NaN
* The bit in an unpacked double which indicates that it is a quiet NaN
*/
#define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS)) #define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS))
/* // Operations on packed single-precision numbers
* Operations on packed single-precision numbers
*/
#define vfp_double_packed_sign(v) ((v) & (1ULL << 63)) #define vfp_double_packed_sign(v) ((v) & (1ULL << 63))
#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63)) #define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63))
#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63)) #define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63))
#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1)) #define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1)) #define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
/* // Unpack a double-precision float. Note that this returns the magnitude
* Unpack a double-precision float. Note that this returns the magnitude // of the double-precision float mantissa with the 1. if necessary,
* of the double-precision float mantissa with the 1. if necessary, // aligned to bit 62.
* aligned to bit 62. static inline void vfp_double_unpack(vfp_double* s, s64 val)
*/
static inline void vfp_double_unpack(struct vfp_double *s, s64 val)
{ {
u64 significand; u64 significand;
@ -385,11 +352,9 @@ static inline void vfp_double_unpack(struct vfp_double *s, s64 val)
s->significand = significand; s->significand = significand;
} }
/* // Re-pack a double-precision float. This assumes that the float is
* Re-pack a double-precision float. This assumes that the float is // already normalised such that the MSB is bit 30, _not_ bit 31.
* already normalised such that the MSB is bit 30, _not_ bit 31. static inline s64 vfp_double_pack(vfp_double* s)
*/
static inline s64 vfp_double_pack(struct vfp_double *s)
{ {
u64 val = ((u64)s->sign << 48) + u64 val = ((u64)s->sign << 48) +
((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) + ((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
@ -397,7 +362,7 @@ static inline s64 vfp_double_pack(struct vfp_double *s)
return (s64)val; return (s64)val;
} }
static inline int vfp_double_type(struct vfp_double *s) static inline int vfp_double_type(vfp_double* s)
{ {
int type = VFP_NUMBER; int type = VFP_NUMBER;
if (s->exponent == 2047) { if (s->exponent == 2047) {
@ -416,34 +381,30 @@ static inline int vfp_double_type(struct vfp_double *s)
return type; return type;
} }
u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func); u32 vfp_double_normaliseround(ARMul_State* state, int dd, vfp_double* vd, u32 fpscr, u32 exceptions, const char* func);
u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand); u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
/* // A special flag to tell the normalisation code not to normalise.
* A special flag to tell the normalisation code not to normalise.
*/
#define VFP_NAN_FLAG 0x100 #define VFP_NAN_FLAG 0x100
/* // A bit pattern used to indicate the initial (unset) value of the
* A bit pattern used to indicate the initial (unset) value of the // exception mask, in case nothing handles an instruction. This
* exception mask, in case nothing handles an instruction. This // doesn't include the NAN flag, which get masked out before
* doesn't include the NAN flag, which get masked out before // we check for an error.
* we check for an error.
*/
#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG) #define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
/* // A flag to tell vfp instruction type.
* A flag to tell vfp instruction type. // OP_SCALAR - This operation always operates in scalar mode
* OP_SCALAR - this operation always operates in scalar mode // OP_SD - The instruction exceptionally writes to a single precision result.
* OP_SD - the instruction exceptionally writes to a single precision result. // OP_DD - The instruction exceptionally writes to a double precision result.
* OP_DD - the instruction exceptionally writes to a double precision result. // OP_SM - The instruction exceptionally reads from a single precision operand.
* OP_SM - the instruction exceptionally reads from a single precision operand. enum : u32 {
*/ OP_SCALAR = (1 << 0),
#define OP_SCALAR (1 << 0) OP_SD = (1 << 1),
#define OP_SD (1 << 1) OP_DD = (1 << 1),
#define OP_DD (1 << 1) OP_SM = (1 << 2)
#define OP_SM (1 << 2) };
struct op { struct op {
u32 (* const fn)(ARMul_State* state, int dd, int dn, int dm, u32 fpscr); u32 (* const fn)(ARMul_State* state, int dd, int dn, int dm, u32 fpscr);
@ -480,7 +441,7 @@ static inline u32 fls(ARMword x)
} }
u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func); u32 vfp_double_normaliseroundintern(ARMul_State* state, vfp_double* vd, u32 fpscr, u32 exceptions, const char* func);
u32 vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr); u32 vfp_double_multiply(vfp_double* vdd, vfp_double* vdn, vfp_double* vdm, u32 fpscr);
u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr); u32 vfp_double_add(vfp_double* vdd, vfp_double* vdn, vfp_double *vdm, u32 fpscr);
u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr); u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, vfp_double* dm, u32 fpscr);

14
src/core/arm/skyeye_common/vfp/vfpdouble.cpp
View File

@ -511,7 +511,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
LOG_TRACE(Core_ARM11, "In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr); LOG_TRACE(Core_ARM11, "In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
m = vfp_get_double(state, dm); m = vfp_get_double(state, dm);
if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) { if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
ret |= FPSCR_C | FPSCR_V; ret |= FPSCR_CFLAG | FPSCR_VFLAG;
if (signal_on_qnan || !(vfp_double_packed_mantissa(m) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) if (signal_on_qnan || !(vfp_double_packed_mantissa(m) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1))))
/* /*
* Signalling NaN, or signalling on quiet NaN * Signalling NaN, or signalling on quiet NaN
@ -521,7 +521,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
d = vfp_get_double(state, dd); d = vfp_get_double(state, dd);
if (vfp_double_packed_exponent(d) == 2047 && vfp_double_packed_mantissa(d)) { if (vfp_double_packed_exponent(d) == 2047 && vfp_double_packed_mantissa(d)) {
ret |= FPSCR_C | FPSCR_V; ret |= FPSCR_CFLAG | FPSCR_VFLAG;
if (signal_on_qnan || !(vfp_double_packed_mantissa(d) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) if (signal_on_qnan || !(vfp_double_packed_mantissa(d) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1))))
/* /*
* Signalling NaN, or signalling on quiet NaN * Signalling NaN, or signalling on quiet NaN
@ -535,7 +535,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
/* /*
* equal * equal
*/ */
ret |= FPSCR_Z | FPSCR_C; ret |= FPSCR_ZFLAG | FPSCR_CFLAG;
//printf("In %s,1 ret=0x%x\n", __FUNCTION__, ret); //printf("In %s,1 ret=0x%x\n", __FUNCTION__, ret);
} else if (vfp_double_packed_sign(d ^ m)) { } else if (vfp_double_packed_sign(d ^ m)) {
/* /*
@ -545,22 +545,22 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
/* /*
* d is negative, so d < m * d is negative, so d < m
*/ */
ret |= FPSCR_N; ret |= FPSCR_NFLAG;
else else
/* /*
* d is positive, so d > m * d is positive, so d > m
*/ */
ret |= FPSCR_C; ret |= FPSCR_CFLAG;
} else if ((vfp_double_packed_sign(d) != 0) ^ (d < m)) { } else if ((vfp_double_packed_sign(d) != 0) ^ (d < m)) {
/* /*
* d < m * d < m
*/ */
ret |= FPSCR_N; ret |= FPSCR_NFLAG;
} else if ((vfp_double_packed_sign(d) != 0) ^ (d > m)) { } else if ((vfp_double_packed_sign(d) != 0) ^ (d > m)) {
/* /*
* d > m * d > m
*/ */
ret |= FPSCR_C; ret |= FPSCR_CFLAG;
} }
} }
LOG_TRACE(Core_ARM11, "In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret); LOG_TRACE(Core_ARM11, "In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret);

14
src/core/arm/skyeye_common/vfp/vfpsingle.cpp
View File

@ -419,7 +419,7 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3
d = vfp_get_float(state, sd); d = vfp_get_float(state, sd);
if (vfp_single_packed_exponent(m) == 255 && vfp_single_packed_mantissa(m)) { if (vfp_single_packed_exponent(m) == 255 && vfp_single_packed_mantissa(m)) {
ret |= FPSCR_C | FPSCR_V; ret |= FPSCR_CFLAG | FPSCR_VFLAG;
if (signal_on_qnan || !(vfp_single_packed_mantissa(m) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) if (signal_on_qnan || !(vfp_single_packed_mantissa(m) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1))))
/* /*
* Signalling NaN, or signalling on quiet NaN * Signalling NaN, or signalling on quiet NaN
@ -428,7 +428,7 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3
} }
if (vfp_single_packed_exponent(d) == 255 && vfp_single_packed_mantissa(d)) { if (vfp_single_packed_exponent(d) == 255 && vfp_single_packed_mantissa(d)) {
ret |= FPSCR_C | FPSCR_V; ret |= FPSCR_CFLAG | FPSCR_VFLAG;
if (signal_on_qnan || !(vfp_single_packed_mantissa(d) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) if (signal_on_qnan || !(vfp_single_packed_mantissa(d) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1))))
/* /*
* Signalling NaN, or signalling on quiet NaN * Signalling NaN, or signalling on quiet NaN
@ -441,7 +441,7 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3
/* /*
* equal * equal
*/ */
ret |= FPSCR_Z | FPSCR_C; ret |= FPSCR_ZFLAG | FPSCR_CFLAG;
} else if (vfp_single_packed_sign(d ^ m)) { } else if (vfp_single_packed_sign(d ^ m)) {
/* /*
* different signs * different signs
@ -450,22 +450,22 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3
/* /*
* d is negative, so d < m * d is negative, so d < m
*/ */
ret |= FPSCR_N; ret |= FPSCR_NFLAG;
else else
/* /*
* d is positive, so d > m * d is positive, so d > m
*/ */
ret |= FPSCR_C; ret |= FPSCR_CFLAG;
} else if ((vfp_single_packed_sign(d) != 0) ^ (d < m)) { } else if ((vfp_single_packed_sign(d) != 0) ^ (d < m)) {
/* /*
* d < m * d < m
*/ */
ret |= FPSCR_N; ret |= FPSCR_NFLAG;
} else if ((vfp_single_packed_sign(d) != 0) ^ (d > m)) { } else if ((vfp_single_packed_sign(d) != 0) ^ (d > m)) {
/* /*
* d > m * d > m
*/ */
ret |= FPSCR_C; ret |= FPSCR_CFLAG;
} }
} }
return ret; return ret;