Merge pull request #3184 from MerryMage/timing
core/arm: Improve timing accuracy before service calls in JIT
This commit is contained in:
commit
e165b5bb94
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@ -1 +1 @@
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Subproject commit dfbd3912a4b8e0d28e1a4045893a750f0107fbaa
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Subproject commit f343c56268ef3f8fbed5bbc513fbc56430a47255
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@ -24,19 +24,11 @@ public:
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u32 fpexc;
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u32 fpexc;
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};
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};
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/**
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/// Runs the CPU until an event happens
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* Runs the CPU for the given number of instructions
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virtual void Run() = 0;
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* @param num_instructions Number of instructions to run
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*/
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void Run(int num_instructions) {
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ExecuteInstructions(num_instructions);
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this->num_instructions += num_instructions;
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}
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/// Step CPU by one instruction
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/// Step CPU by one instruction
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void Step() {
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virtual void Step() = 0;
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Run(1);
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}
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/// Clear all instruction cache
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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virtual void ClearInstructionCache() = 0;
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@ -138,19 +130,4 @@ public:
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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virtual void PrepareReschedule() = 0;
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/// Getter for num_instructions
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u64 GetNumInstructions() const {
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return num_instructions;
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}
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protected:
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/**
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* Executes the given number of instructions
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* @param num_instructions Number of instructions to executes
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*/
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virtual void ExecuteInstructions(int num_instructions) = 0;
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private:
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u64 num_instructions = 0; ///< Number of instructions executed
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};
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};
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@ -40,11 +40,20 @@ static bool IsReadOnlyMemory(u32 vaddr) {
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return false;
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return false;
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}
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}
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static void AddTicks(u64 ticks) {
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CoreTiming::AddTicks(ticks);
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}
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static u64 GetTicksRemaining() {
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int ticks = CoreTiming::GetDowncount();
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return static_cast<u64>(ticks <= 0 ? 0 : ticks);
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}
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static Dynarmic::UserCallbacks GetUserCallbacks(
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static Dynarmic::UserCallbacks GetUserCallbacks(
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const std::shared_ptr<ARMul_State>& interpeter_state, Memory::PageTable* current_page_table) {
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const std::shared_ptr<ARMul_State>& interpreter_state, Memory::PageTable* current_page_table) {
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Dynarmic::UserCallbacks user_callbacks{};
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Dynarmic::UserCallbacks user_callbacks{};
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user_callbacks.InterpreterFallback = &InterpreterFallback;
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user_callbacks.InterpreterFallback = &InterpreterFallback;
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user_callbacks.user_arg = static_cast<void*>(interpeter_state.get());
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user_callbacks.user_arg = static_cast<void*>(interpreter_state.get());
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user_callbacks.CallSVC = &SVC::CallSVC;
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user_callbacks.CallSVC = &SVC::CallSVC;
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user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
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user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
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user_callbacks.memory.ReadCode = &Memory::Read32;
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user_callbacks.memory.ReadCode = &Memory::Read32;
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@ -56,8 +65,10 @@ static Dynarmic::UserCallbacks GetUserCallbacks(
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user_callbacks.memory.Write16 = &Memory::Write16;
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user_callbacks.memory.Write16 = &Memory::Write16;
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user_callbacks.memory.Write32 = &Memory::Write32;
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user_callbacks.memory.Write32 = &Memory::Write32;
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user_callbacks.memory.Write64 = &Memory::Write64;
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user_callbacks.memory.Write64 = &Memory::Write64;
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user_callbacks.AddTicks = &AddTicks;
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user_callbacks.GetTicksRemaining = &GetTicksRemaining;
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user_callbacks.page_table = ¤t_page_table->pointers;
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user_callbacks.page_table = ¤t_page_table->pointers;
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user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpeter_state);
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user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpreter_state);
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return user_callbacks;
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return user_callbacks;
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}
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}
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@ -66,6 +77,19 @@ ARM_Dynarmic::ARM_Dynarmic(PrivilegeMode initial_mode) {
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PageTableChanged();
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PageTableChanged();
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}
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}
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MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
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void ARM_Dynarmic::Run() {
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ASSERT(Memory::GetCurrentPageTable() == current_page_table);
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MICROPROFILE_SCOPE(ARM_Jit);
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jit->Run(GetTicksRemaining());
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}
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void ARM_Dynarmic::Step() {
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InterpreterFallback(jit->Regs()[15], jit, static_cast<void*>(interpreter_state.get()));
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}
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void ARM_Dynarmic::SetPC(u32 pc) {
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void ARM_Dynarmic::SetPC(u32 pc) {
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jit->Regs()[15] = pc;
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jit->Regs()[15] = pc;
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}
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}
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@ -124,17 +148,6 @@ void ARM_Dynarmic::SetCP15Register(CP15Register reg, u32 value) {
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interpreter_state->CP15[reg] = value;
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interpreter_state->CP15[reg] = value;
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}
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}
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MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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ASSERT(Memory::GetCurrentPageTable() == current_page_table);
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MICROPROFILE_SCOPE(ARM_Jit);
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std::size_t ticks_executed = jit->Run(static_cast<unsigned>(num_instructions));
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CoreTiming::AddTicks(ticks_executed);
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}
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, jit->Regs().data(), sizeof(ctx.cpu_registers));
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memcpy(ctx.cpu_registers, jit->Regs().data(), sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
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memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
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@ -168,6 +181,7 @@ void ARM_Dynarmic::PrepareReschedule() {
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}
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}
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void ARM_Dynarmic::ClearInstructionCache() {
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void ARM_Dynarmic::ClearInstructionCache() {
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// TODO: Clear interpreter cache when appropriate.
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for (const auto& j : jits) {
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for (const auto& j : jits) {
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j.second->ClearCache();
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j.second->ClearCache();
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}
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}
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@ -19,6 +19,9 @@ class ARM_Dynarmic final : public ARM_Interface {
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public:
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public:
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ARM_Dynarmic(PrivilegeMode initial_mode);
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ARM_Dynarmic(PrivilegeMode initial_mode);
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void Run() override;
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void Step() override;
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void SetPC(u32 pc) override;
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void SetPC(u32 pc) override;
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u32 GetPC() const override;
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u32 GetPC() const override;
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u32 GetReg(int index) const override;
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u32 GetReg(int index) const override;
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@ -36,7 +39,6 @@ public:
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void LoadContext(const ThreadContext& ctx) override;
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void LoadContext(const ThreadContext& ctx) override;
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void PrepareReschedule() override;
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void PrepareReschedule() override;
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void ExecuteInstructions(int num_instructions) override;
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void ClearInstructionCache() override;
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void ClearInstructionCache() override;
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void PageTableChanged() override;
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void PageTableChanged() override;
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstring>
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#include <cstring>
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#include <memory>
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#include <memory>
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#include "core/arm/dyncom/arm_dyncom.h"
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#include "core/arm/dyncom/arm_dyncom.h"
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@ -20,6 +21,14 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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ARM_DynCom::~ARM_DynCom() {}
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ARM_DynCom::~ARM_DynCom() {}
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void ARM_DynCom::Run() {
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ExecuteInstructions(std::max(CoreTiming::GetDowncount(), 0));
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}
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void ARM_DynCom::Step() {
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ExecuteInstructions(1);
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}
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void ARM_DynCom::ClearInstructionCache() {
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void ARM_DynCom::ClearInstructionCache() {
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state->instruction_cache.clear();
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state->instruction_cache.clear();
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trans_cache_buf_top = 0;
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trans_cache_buf_top = 0;
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@ -79,10 +88,6 @@ void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions;
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state->NumInstrsToExecute = num_instructions;
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// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
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// executing one instruction at a time. Otherwise, if a block is being executed, more
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// instructions may actually be executed than specified.
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unsigned ticks_executed = InterpreterMainLoop(state.get());
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unsigned ticks_executed = InterpreterMainLoop(state.get());
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CoreTiming::AddTicks(ticks_executed);
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CoreTiming::AddTicks(ticks_executed);
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}
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}
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@ -15,6 +15,9 @@ public:
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ARM_DynCom(PrivilegeMode initial_mode);
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ARM_DynCom(PrivilegeMode initial_mode);
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~ARM_DynCom();
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~ARM_DynCom();
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void Run() override;
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void Step() override;
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void ClearInstructionCache() override;
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void ClearInstructionCache() override;
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void PageTableChanged() override;
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void PageTableChanged() override;
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@ -35,8 +38,9 @@ public:
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void LoadContext(const ThreadContext& ctx) override;
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void LoadContext(const ThreadContext& ctx) override;
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void PrepareReschedule() override;
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void PrepareReschedule() override;
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void ExecuteInstructions(int num_instructions) override;
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private:
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private:
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void ExecuteInstructions(int num_instructions);
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std::unique_ptr<ARMul_State> state;
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std::unique_ptr<ARMul_State> state;
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};
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};
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@ -18,6 +18,7 @@
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/arm/skyeye_common/armsupp.h"
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#include "core/arm/skyeye_common/armsupp.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/core_timing.h"
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#include "core/gdbstub/gdbstub.h"
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#include "core/gdbstub/gdbstub.h"
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#include "core/hle/svc.h"
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#include "core/hle/svc.h"
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#include "core/memory.h"
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#include "core/memory.h"
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@ -3858,6 +3859,10 @@ SUB_INST : {
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SWI_INST : {
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SWI_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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swi_inst* const inst_cream = (swi_inst*)inst_base->component;
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swi_inst* const inst_cream = (swi_inst*)inst_base->component;
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CoreTiming::AddTicks(num_instrs);
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cpu->NumInstrsToExecute =
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num_instrs >= cpu->NumInstrsToExecute ? 0 : cpu->NumInstrsToExecute - num_instrs;
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num_instrs = 0;
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SVC::CallSVC(inst_cream->num & 0xFFFF);
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SVC::CallSVC(inst_cream->num & 0xFFFF);
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}
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}
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@ -27,7 +27,7 @@ namespace Core {
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/*static*/ System System::s_instance;
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/*static*/ System System::s_instance;
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System::ResultStatus System::RunLoop(int tight_loop) {
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System::ResultStatus System::RunLoop(bool tight_loop) {
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status = ResultStatus::Success;
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status = ResultStatus::Success;
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if (!cpu_core) {
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if (!cpu_core) {
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return ResultStatus::ErrorNotInitialized;
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return ResultStatus::ErrorNotInitialized;
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@ -57,7 +57,11 @@ System::ResultStatus System::RunLoop(int tight_loop) {
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PrepareReschedule();
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PrepareReschedule();
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} else {
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} else {
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CoreTiming::Advance();
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CoreTiming::Advance();
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cpu_core->Run(tight_loop);
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if (tight_loop) {
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cpu_core->Run();
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} else {
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cpu_core->Step();
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}
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}
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}
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HW::Update();
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HW::Update();
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@ -67,7 +71,7 @@ System::ResultStatus System::RunLoop(int tight_loop) {
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}
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}
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System::ResultStatus System::SingleStep() {
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System::ResultStatus System::SingleStep() {
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return RunLoop(1);
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return RunLoop(false);
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}
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}
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System::ResultStatus System::Load(EmuWindow* emu_window, const std::string& filepath) {
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System::ResultStatus System::Load(EmuWindow* emu_window, const std::string& filepath) {
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@ -50,10 +50,10 @@ public:
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* is not required to do a full dispatch with each instruction. NOTE: the number of instructions
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* is not required to do a full dispatch with each instruction. NOTE: the number of instructions
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* requested is not guaranteed to run, as this will be interrupted preemptively if a hardware
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* requested is not guaranteed to run, as this will be interrupted preemptively if a hardware
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* update is requested (e.g. on a thread switch).
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* update is requested (e.g. on a thread switch).
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* @param tight_loop Number of instructions to execute.
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* @param tight_loop If false, the CPU single-steps.
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* @return Result status, indicating whethor or not the operation succeeded.
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* @return Result status, indicating whethor or not the operation succeeded.
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*/
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*/
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ResultStatus RunLoop(int tight_loop = 1000);
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ResultStatus RunLoop(bool tight_loop = true);
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/**
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/**
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* Step the CPU one instruction
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* Step the CPU one instruction
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@ -34,7 +34,7 @@ TEST_CASE("ARM_DynCom (vfp): vadd", "[arm_dyncom]") {
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dyncom.SetVFPSystemReg(VFP_FPSCR, test_case.initial_fpscr);
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dyncom.SetVFPSystemReg(VFP_FPSCR, test_case.initial_fpscr);
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dyncom.SetVFPReg(4, test_case.a);
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dyncom.SetVFPReg(4, test_case.a);
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dyncom.SetVFPReg(6, test_case.b);
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dyncom.SetVFPReg(6, test_case.b);
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dyncom.ExecuteInstructions(1);
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dyncom.Step();
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if (dyncom.GetVFPReg(2) != test_case.result ||
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if (dyncom.GetVFPReg(2) != test_case.result ||
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dyncom.GetVFPSystemReg(VFP_FPSCR) != test_case.final_fpscr) {
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dyncom.GetVFPSystemReg(VFP_FPSCR) != test_case.final_fpscr) {
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printf("f: %x\n", test_case.initial_fpscr);
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printf("f: %x\n", test_case.initial_fpscr);
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