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Cleanup: Logging in Core

This commit is contained in:
Chin 2015-01-04 13:59:34 -05:00 committed by chinhodado
parent be8f665142
commit fa8e6272c8
5 changed files with 274 additions and 600 deletions
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45
src/core/arm/interpreter/armemu.cpp
View File

@ -340,7 +340,6 @@ ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
mem_Dbugdump(); mem_Dbugdump();
}*/ }*/
/*if (pc == 0x0022D168) /*if (pc == 0x0022D168)
{ {
int j = 0; int j = 0;
@ -1117,7 +1116,6 @@ ARMul_Emulate26 (ARMul_State * state)
//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... //chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
/* Actual execution of instructions begins here. */ /* Actual execution of instructions begins here. */
/* If the condition codes don't match, stop here. */ /* If the condition codes don't match, stop here. */
if (temp) { if (temp) {
@ -1178,8 +1176,6 @@ mainswitch:
tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
dst = ((data >> msb) << (msb - lsb)); dst = ((data >> msb) << (msb - lsb));
dst = (dst << lsb) | tmp_rd; dst = (dst << lsb) | tmp_rd;
/*SKYEYE_DBG("BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
msb, lsb, Rd, state->Reg[Rd], dst);*/
goto donext; goto donext;
} // bfc instr } // bfc instr
else if (((msb >= lsb) && (msb < 32))) { else if (((msb >= lsb) && (msb < 32))) {
@ -1189,8 +1185,6 @@ mainswitch:
tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
dst = ((data >> msb) << (msb - lsb)) | tmp_rn; dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
dst = (dst << lsb) | tmp_rd; dst = (dst << lsb) | tmp_rd;
/*SKYEYE_DBG("BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);*/
goto donext; goto donext;
} // bfi instr } // bfi instr
} }
@ -2215,10 +2209,8 @@ mainswitch:
state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4)) state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4))
enter = true; enter = true;
//todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html //todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html
if (enter) { if (enter) {
ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]); ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]);
ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]); ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]);
@ -2254,9 +2246,6 @@ mainswitch:
LHPREUPWB (); LHPREUPWB ();
/* Continue with remaining instruction decoding. */ /* Continue with remaining instruction decoding. */
#endif #endif
dest = DPSRegRHS; dest = DPSRegRHS;
WRITESDEST (dest); WRITESDEST (dest);
@ -2296,7 +2285,6 @@ mainswitch:
temp = LHS + GetLS7RHS (state, instr); temp = LHS + GetLS7RHS (state, instr);
LoadHalfWord (state, instr, temp, LSIGNED); LoadHalfWord (state, instr, temp, LSIGNED);
break; break;
} }
if (BITS (4, 7) == 0xb) { if (BITS (4, 7) == 0xb) {
/* LDRH immediate offset, no write-back, up, pre indexed. */ /* LDRH immediate offset, no write-back, up, pre indexed. */
@ -2321,7 +2309,6 @@ mainswitch:
} }
/* LDR immediate offset, no write-back, up, pre indexed. */ /* LDR immediate offset, no write-back, up, pre indexed. */
LHPREUP (); LHPREUP ();
} }
#endif #endif
@ -2342,7 +2329,6 @@ mainswitch:
if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true; if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
//StoreWord(state, lhs, RHS) //StoreWord(state, lhs, RHS)
if (state->Aborted) { if (state->Aborted) {
TAKEABORT; TAKEABORT;
@ -2396,7 +2382,6 @@ mainswitch:
WRITESDEST (dest); WRITESDEST (dest);
break; break;
/* Data Processing Immediate RHS Instructions. */ /* Data Processing Immediate RHS Instructions. */
case 0x20: /* AND immed */ case 0x20: /* AND immed */
@ -2553,8 +2538,6 @@ mainswitch:
dest = BITS(16, 19); dest = BITS(16, 19);
dest = ((dest<<12) | BITS(0, 11)); dest = ((dest<<12) | BITS(0, 11));
WRITEDEST(dest); WRITEDEST(dest);
//SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
// __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
break; break;
} else { } else {
UNDEF_Test; UNDEF_Test;
@ -2717,7 +2700,6 @@ mainswitch:
WRITESDEST (~rhs); WRITESDEST (~rhs);
break; break;
/* Single Data Transfer Immediate RHS Instructions. */ /* Single Data Transfer Immediate RHS Instructions. */
case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
@ -2849,7 +2831,6 @@ mainswitch:
state->NtransSig = (state->Mode & 3) ? HIGH : LOW; state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break; break;
case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
(void) StoreWord (state, instr, LHS - LSImmRHS); (void) StoreWord (state, instr, LHS - LSImmRHS);
break; break;
@ -2946,7 +2927,6 @@ mainswitch:
LSBase = temp; LSBase = temp;
break; break;
/* Single Data Transfer Register RHS Instructions. */ /* Single Data Transfer Register RHS Instructions. */
case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
@ -3234,11 +3214,9 @@ mainswitch:
int Rm = 0; int Rm = 0;
/* utxb */ /* utxb */
if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) { if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
Rm = (RHS >> (8 * BITS(10, 11))) & 0xff; Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
DEST = Rm; DEST = Rm;
} }
} }
#endif #endif
if (BIT (4)) { if (BIT (4)) {
@ -3285,7 +3263,6 @@ mainswitch:
state->NtransSig = (state->Mode & 3) ? HIGH : LOW; state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break; break;
case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
if (BIT (4)) { if (BIT (4)) {
#ifdef MODE32 #ifdef MODE32
@ -3489,7 +3466,6 @@ mainswitch:
LSBase = temp; LSBase = temp;
break; break;
/* Multiple Data Transfer Instructions. */ /* Multiple Data Transfer Instructions. */
case 0x80: /* Store, No WriteBack, Post Dec. */ case 0x80: /* Store, No WriteBack, Post Dec. */
@ -3636,7 +3612,6 @@ mainswitch:
LOADSMULT (instr, temp + 4L, temp + LSMNumRegs); LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
break; break;
/* Branch forward. */ /* Branch forward. */
case 0xa0: case 0xa0:
case 0xa1: case 0xa1:
@ -3650,7 +3625,6 @@ mainswitch:
FLUSHPIPE; FLUSHPIPE;
break; break;
/* Branch backward. */ /* Branch backward. */
case 0xa8: case 0xa8:
case 0xa9: case 0xa9:
@ -3664,7 +3638,6 @@ mainswitch:
FLUSHPIPE; FLUSHPIPE;
break; break;
/* Branch and Link forward. */ /* Branch and Link forward. */
case 0xb0: case 0xb0:
case 0xb1: case 0xb1:
@ -3690,10 +3663,8 @@ mainswitch:
printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
#endif #endif
break; break;
/* Branch and Link backward. */ /* Branch and Link backward. */
case 0xb8: case 0xb8:
case 0xb9: case 0xb9:
@ -3712,18 +3683,14 @@ mainswitch:
state->Reg[15] = pc + 8 + NEGBRANCH; state->Reg[15] = pc + 8 + NEGBRANCH;
FLUSHPIPE; FLUSHPIPE;
#ifdef callstacker #ifdef callstacker
memset(a, 0, 256); memset(a, 0, 256);
aufloeser(a, state->Reg[15]); aufloeser(a, state->Reg[15]);
printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
#endif #endif
break; break;
/* Co-Processor Data Transfers. */ /* Co-Processor Data Transfers. */
case 0xc4: case 0xc4:
if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0 if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
@ -3859,7 +3826,6 @@ mainswitch:
ARMul_LDC (state, instr, lhs); ARMul_LDC (state, instr, lhs);
break; break;
/* Co-Processor Register Transfers (MCR) and Data Ops. */ /* Co-Processor Register Transfers (MCR) and Data Ops. */
case 0xe2: case 0xe2:
@ -3891,7 +3857,6 @@ mainswitch:
ARMul_CDP (state, instr); ARMul_CDP (state, instr);
break; break;
/* Co-Processor Register Transfers (MRC) and Data Ops. */ /* Co-Processor Register Transfers (MRC) and Data Ops. */
case 0xe1: case 0xe1:
case 0xe3: case 0xe3:
@ -3916,7 +3881,6 @@ mainswitch:
ARMul_CDP (state, instr); ARMul_CDP (state, instr);
break; break;
/* SWI instruction. */ /* SWI instruction. */
case 0xf0: case 0xf0:
case 0xf1: case 0xf1:
@ -4118,7 +4082,6 @@ TEST_EMULATE:
// continue; // continue;
else if (state->Emulate != RUN) else if (state->Emulate != RUN)
break; break;
} }
while (state->NumInstrsToExecute); while (state->NumInstrsToExecute);
@ -4156,7 +4119,6 @@ exit:
static FILE *fd; static FILE *fd;
/*if (!init) { /*if (!init) {
fd = fopen("./pc.txt", "w"); fd = fopen("./pc.txt", "w");
if (!fd) { if (!fd) {
exit(-1); exit(-1);
@ -4725,8 +4687,6 @@ out:
address, DEST); \ address, DEST); \
} }
static unsigned static unsigned
LoadWord (ARMul_State * state, ARMword instr, ARMword address) { LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
ARMword dest; ARMword dest;
@ -5158,7 +5118,6 @@ out:
/*chy 2004-05-23 chy goto end */ /*chy 2004-05-23 chy goto end */
if (state->Aborted) if (state->Aborted)
goto L_ldm_makeabort; goto L_ldm_makeabort;
} }
if (BIT (15) && !state->Aborted) if (BIT (15) && !state->Aborted)
@ -5202,7 +5161,6 @@ L_ldm_makeabort:
LSBase = WBBase; LSBase = WBBase;
} }
/* chy 2005-11-24, over */ /* chy 2005-11-24, over */
} }
/* This function does the work of loading the registers listed in an LDM /* This function does the work of loading the registers listed in an LDM
@ -5405,7 +5363,6 @@ L_ldm_s_makeabort:
//chy 2004-05-23, needn't store other when aborted //chy 2004-05-23, needn't store other when aborted
if (state->Aborted) if (state->Aborted)
goto L_stm_takeabort; goto L_stm_takeabort;
} }
//chy 2004-05-23,should compare the Abort Models //chy 2004-05-23,should compare the Abort Models
@ -5508,7 +5465,6 @@ L_stm_takeabort:
/* Restore the correct bank. */ /* Restore the correct bank. */
(void) ARMul_SwitchMode (state, USER26MODE, state->Mode); (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
//chy 2004-05-23,should compare the Abort Models //chy 2004-05-23,should compare the Abort Models
L_stm_s_takeabort: L_stm_s_takeabort:
if (BIT (21) && LHSReg != 15) { if (BIT (21) && LHSReg != 15) {
@ -5763,7 +5719,6 @@ L_stm_s_takeabort:
TAKEABORT; TAKEABORT;
} }
if (enter) { if (enter) {
ARMul_StoreByte(state, lhs, RHS); ARMul_StoreByte(state, lhs, RHS);
state->Reg[DESTReg] = 0; state->Reg[DESTReg] = 0;

149
src/core/arm/skyeye_common/vfp/vfp.cpp
View File

@ -20,16 +20,11 @@
/* Note: this file handles interface with arm core and vfp registers */ /* Note: this file handles interface with arm core and vfp registers */
/* Opens debug for classic interpreter only */
//#define DEBUG
#include "common/common.h" #include "common/common.h"
#include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/vfp/vfp.h" #include "core/arm/skyeye_common/vfp/vfp.h"
#define DEBUG DBG
//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */ //ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
unsigned VFPInit(ARMul_State* state) unsigned VFPInit(ARMul_State* state)
@ -75,7 +70,7 @@ unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value)
return ARMul_DONE; return ARMul_DONE;
} }
} }
DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
return ARMul_CANT; return ARMul_CANT;
@ -122,7 +117,7 @@ unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value)
return ARMul_DONE; return ARMul_DONE;
} }
} }
DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
return ARMul_CANT; return ARMul_CANT;
@ -152,7 +147,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32*
return ARMul_DONE; return ARMul_DONE;
} }
} }
DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
instr, CoProc, OPC_1, Rt, Rt2, CRm); instr, CoProc, OPC_1, Rt, Rt2, CRm);
return ARMul_CANT; return ARMul_CANT;
@ -186,7 +181,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v
return ARMul_DONE; return ARMul_DONE;
} }
} }
DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
instr, CoProc, OPC_1, Rt, Rt2, CRm); instr, CoProc, OPC_1, Rt, Rt2, CRm);
return ARMul_CANT; return ARMul_CANT;
@ -208,17 +203,17 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
/* VSTM */ /* VSTM */
if ( (P|U|D|W) == 0 ) { if ( (P|U|D|W) == 0 ) {
DEBUG("In %s, UNDEFINED\n", __FUNCTION__); LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
exit(-1); exit(-1);
} }
if (CoProc == 10 || CoProc == 11) { if (CoProc == 10 || CoProc == 11) {
#if 1 #if 1
if (P == 0 && U == 0 && W == 0) { if (P == 0 && U == 0 && W == 0) {
DEBUG("VSTM Related encodings\n"); LOG_ERROR(Core_ARM11, "VSTM Related encodings\n");
exit(-1); exit(-1);
} }
if (P == U && W == 1) { if (P == U && W == 1) {
DEBUG("UNDEFINED\n"); LOG_ERROR(Core_ARM11, "UNDEFINED\n");
exit(-1); exit(-1);
} }
#endif #endif
@ -235,7 +230,7 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
return VSTM(state, type, instr, value); return VSTM(state, type, instr, value);
} }
DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
instr, CoProc, CRd, Rn, imm8, P, U, D, W); instr, CoProc, CRd, Rn, imm8, P, U, D, W);
return ARMul_CANT; return ARMul_CANT;
@ -256,7 +251,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
/* TODO check access permission */ /* TODO check access permission */
if ( (P|U|D|W) == 0 ) { if ( (P|U|D|W) == 0 ) {
DEBUG("In %s, UNDEFINED\n", __FUNCTION__); LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
exit(-1); exit(-1);
} }
if (CoProc == 10 || CoProc == 11) if (CoProc == 10 || CoProc == 11)
@ -273,7 +268,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
return VLDM(state, type, instr, value); return VLDM(state, type, instr, value);
} }
DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n", LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
instr, CoProc, CRd, Rn, imm8, P, U, D, W); instr, CoProc, CRd, Rn, imm8, P, U, D, W);
return ARMul_CANT; return ARMul_CANT;
@ -340,33 +335,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
if (CoProc == 10 || CoProc == 11) if (CoProc == 10 || CoProc == 11)
{ {
if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 0)
DBG("VMLA :\n");
if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 2)
DBG("VMLS :\n");
if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 2)
DBG("VNMLA :\n");
if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 0)
DBG("VNMLS :\n");
if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 2)
DBG("VNMUL :\n");
if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 0)
DBG("VMUL :\n");
if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 0)
DBG("VADD :\n");
if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 2)
DBG("VSUB :\n");
if ((OPC_1 & 0xB) == 0xA && (OPC_2 & 0x2) == 0)
DBG("VDIV :\n");
if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0) if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0)
{ {
unsigned int single = BIT(8) == 0; unsigned int single = BIT(8) == 0;
@ -392,30 +360,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
return ARMul_DONE; return ARMul_DONE;
} }
if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x7) == 6)
DBG("VABS :\n");
if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 2)
DBG("VNEG :\n");
if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 6)
DBG("VSQRT :\n");
if ((OPC_1 & 0xB) == 0xB && CRn == 4 && (OPC_2 & 0x2) == 2)
DBG("VCMP(1) :\n");
if ((OPC_1 & 0xB) == 0xB && CRn == 5 && (OPC_2 & 0x2) == 2 && CRm == 0)
DBG("VCMP(2) :\n");
if ((OPC_1 & 0xB) == 0xB && CRn == 7 && (OPC_2 & 0x6) == 6)
DBG("VCVT(BDS) :\n");
if ((OPC_1 & 0xB) == 0xB && CRn >= 0xA && (OPC_2 & 0x2) == 2)
DBG("VCVT(BFF) :\n");
if ((OPC_1 & 0xB) == 0xB && CRn > 7 && (OPC_2 & 0x2) == 2)
DBG("VCVT(BFI) :\n");
int exceptions = 0; int exceptions = 0;
if (CoProc == 10) if (CoProc == 10)
exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]); exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
@ -426,40 +370,33 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
return ARMul_DONE; return ARMul_DONE;
} }
DEBUG("Can't identify %x\n", instr); LOG_WARNING(Core_ARM11, "Can't identify %x\n", instr);
return ARMul_CANT; return ARMul_CANT;
} }
/* ----------- MRC ------------ */ /* ----------- MRC ------------ */
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value) void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
{ {
DBG("VMOV(BRS) :\n");
if (to_arm) if (to_arm)
{ {
DBG("\tr%d <= s%d=[%x]\n", t, n, state->ExtReg[n]);
*value = state->ExtReg[n]; *value = state->ExtReg[n];
} }
else else
{ {
DBG("\ts%d <= r%d=[%x]\n", n, t, *value);
state->ExtReg[n] = *value; state->ExtReg[n] = *value;
} }
} }
void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value) void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
{ {
DBG("VMRS :");
if (reg == 1) if (reg == 1)
{ {
if (Rt != 15) if (Rt != 15)
{ {
*value = state->VFP[VFP_OFFSET(VFP_FPSCR)]; *value = state->VFP[VFP_OFFSET(VFP_FPSCR)];
DBG("\tr%d <= fpscr[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
} }
else else
{ {
*value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ; *value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ;
DBG("\tflags <= fpscr[%1xxxxxxxx]\n", state->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
} }
} }
else else
@ -468,54 +405,46 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
{ {
case 0: case 0:
*value = state->VFP[VFP_OFFSET(VFP_FPSID)]; *value = state->VFP[VFP_OFFSET(VFP_FPSID)];
DBG("\tr%d <= fpsid[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSID)]);
break; break;
case 6: case 6:
/* MVFR1, VFPv3 only ? */ /* MVFR1, VFPv3 only ? */
DBG("\tr%d <= MVFR1 unimplemented\n", Rt); LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
break; break;
case 7: case 7:
/* MVFR0, VFPv3 only? */ /* MVFR0, VFPv3 only? */
DBG("\tr%d <= MVFR0 unimplemented\n", Rt); LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
break; break;
case 8: case 8:
*value = state->VFP[VFP_OFFSET(VFP_FPEXC)]; *value = state->VFP[VFP_OFFSET(VFP_FPEXC)];
DBG("\tr%d <= fpexc[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPEXC)]);
break; break;
default: default:
DBG("\tSUBARCHITECTURE DEFINED\n"); LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n");
break; break;
} }
} }
} }
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
{ {
DBG("VMOV(BRRD) :\n");
if (to_arm) if (to_arm)
{ {
DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n*2+1, n*2, state->ExtReg[n*2+1], state->ExtReg[n*2]);
*value2 = state->ExtReg[n*2+1]; *value2 = state->ExtReg[n*2+1];
*value1 = state->ExtReg[n*2]; *value1 = state->ExtReg[n*2];
} }
else else
{ {
DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n*2+1, n*2, t2, t, *value2, *value1);
state->ExtReg[n*2+1] = *value2; state->ExtReg[n*2+1] = *value2;
state->ExtReg[n*2] = *value1; state->ExtReg[n*2] = *value1;
} }
} }
void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
{ {
DBG("VMOV(BRRSS) :\n");
if (to_arm) if (to_arm)
{ {
DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]);
*value1 = state->ExtReg[n+0]; *value1 = state->ExtReg[n+0];
*value2 = state->ExtReg[n+1]; *value2 = state->ExtReg[n+1];
} }
else else
{ {
DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1);
state->ExtReg[n+0] = *value1; state->ExtReg[n+0] = *value1;
state->ExtReg[n+1] = *value2; state->ExtReg[n+1] = *value2;
} }
@ -526,12 +455,10 @@ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
{ {
if (reg == 1) if (reg == 1)
{ {
DBG("VMSR :\tfpscr <= r%d=[%x]\n", Rt, state->Reg[Rt]);
state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt]; state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt];
} }
else if (reg == 8) else if (reg == 8)
{ {
DBG("VMSR :\tfpexc <= r%d=[%x]\n", Rt, state->Reg[Rt]);
state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt]; state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt];
} }
} }
@ -556,8 +483,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */ d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
n = BITS(16, 19); /* destination register */ n = BITS(16, 19); /* destination register */
DBG("VSTR :\n");
i = 0; i = 0;
regs = 1; regs = 1;
@ -568,7 +493,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_reg) if (single_reg)
{ {
*value = state->ExtReg[d+i]; *value = state->ExtReg[d+i];
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d+i]);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -579,7 +503,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2+i]; *value = state->ExtReg[d*2+i];
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2+i, state->ExtReg[d*2+i]);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -601,10 +524,7 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
imm32 = BITS(0,7)<<2; /* may not be used */ imm32 = BITS(0,7)<<2; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */ regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */
DBG("VPUSH :\n");
DBG("\tsp[%x]", state->Reg[R13]);
state->Reg[R13] = state->Reg[R13] - imm32; state->Reg[R13] = state->Reg[R13] - imm32;
DBG("=>[%x]\n", state->Reg[R13]);
i = 0; i = 0;
@ -615,7 +535,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_regs) if (single_regs)
{ {
*value = state->ExtReg[d + i]; *value = state->ExtReg[d + i];
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -626,7 +545,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2 + i]; *value = state->ExtReg[d*2 + i];
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -651,11 +569,8 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
imm32 = BITS(0,7) * 4; /* may not be used */ imm32 = BITS(0,7) * 4; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */ regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */
DBG("VSTM :\n");
if (wback) { if (wback) {
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32); state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
DBG("\twback r%d[%x]\n", n, state->Reg[n]);
} }
i = 0; i = 0;
@ -667,7 +582,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_regs) if (single_regs)
{ {
*value = state->ExtReg[d + i]; *value = state->ExtReg[d + i];
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -678,7 +592,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2 + i]; *value = state->ExtReg[d*2 + i];
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -702,10 +615,7 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
imm32 = BITS(0,7)<<2; /* may not be used */ imm32 = BITS(0,7)<<2; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */ regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */
DBG("VPOP :\n");
DBG("\tsp[%x]", state->Reg[R13]);
state->Reg[R13] = state->Reg[R13] + imm32; state->Reg[R13] = state->Reg[R13] + imm32;
DBG("=>[%x]\n", state->Reg[R13]);
i = 0; i = 0;
@ -720,7 +630,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_regs) if (single_regs)
{ {
state->ExtReg[d + i] = value; state->ExtReg[d + i] = value;
DBG("\ts%d <= [%x]\n", d + i, value);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -731,7 +640,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2 + i] = value; state->ExtReg[d*2 + i] = value;
DBG("\ts%d <= [%x]\n", d*2 + i, value);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -754,8 +662,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */ d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
n = BITS(16, 19); /* destination register */ n = BITS(16, 19); /* destination register */
DBG("VLDR :\n");
i = 0; i = 0;
regs = 1; regs = 1;
@ -770,7 +676,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_reg) if (single_reg)
{ {
state->ExtReg[d+i] = value; state->ExtReg[d+i] = value;
DBG("\ts%d <= [%x]\n", d+i, value);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -781,7 +686,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2+i] = value; state->ExtReg[d*2+i] = value;
DBG("\ts[%d] <= [%x]\n", d*2+i, value);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -806,11 +710,8 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
imm32 = BITS(0,7) * 4; /* may not be used */ imm32 = BITS(0,7) * 4; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */ regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */
DBG("VLDM :\n");
if (wback) { if (wback) {
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32); state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
DBG("\twback r%d[%x]\n", n, state->Reg[n]);
} }
i = 0; i = 0;
@ -822,7 +723,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_regs) if (single_regs)
{ {
state->ExtReg[d + i] = value; state->ExtReg[d + i] = value;
DBG("\ts%d <= [%x] addr[?]\n", d+i, state->ExtReg[d + i]);
i++; i++;
if (i < regs) if (i < regs)
return ARMul_INC; return ARMul_INC;
@ -833,7 +733,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
{ {
/* FIXME Careful of endianness, may need to rework this */ /* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2 + i] = value; state->ExtReg[d*2 + i] = value;
DBG("\ts[%d] <= [%x] addr[?]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++; i++;
if (i < regs*2) if (i < regs*2)
return ARMul_INC; return ARMul_INC;
@ -848,34 +747,26 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
/* ----------- CDP ------------ */ /* ----------- CDP ------------ */
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm) void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
{ {
DBG("VMOV(I) :\n");
if (single) if (single)
{ {
DBG("\ts%d <= [%x]\n", d, imm);
state->ExtReg[d] = imm; state->ExtReg[d] = imm;
} }
else else
{ {
/* Check endian please */ /* Check endian please */
DBG("\ts[%d-%d] <= [%x-%x]\n", d*2+1, d*2, imm, 0);
state->ExtReg[d*2+1] = imm; state->ExtReg[d*2+1] = imm;
state->ExtReg[d*2] = 0; state->ExtReg[d*2] = 0;
} }
} }
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m) void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
{ {
DBG("VMOV(R) :\n");
if (single) if (single)
{ {
DBG("\ts%d <= s%d[%x]\n", d, m, state->ExtReg[m]);
state->ExtReg[d] = state->ExtReg[m]; state->ExtReg[d] = state->ExtReg[m];
} }
else else
{ {
/* Check endian please */ /* Check endian please */
DBG("\ts[%d-%d] <= s[%d-%d][%x-%x]\n", d*2+1, d*2, m*2+1, m*2, state->ExtReg[m*2+1], state->ExtReg[m*2]);
state->ExtReg[d*2+1] = state->ExtReg[m*2+1]; state->ExtReg[d*2+1] = state->ExtReg[m*2+1];
state->ExtReg[d*2] = state->ExtReg[m*2]; state->ExtReg[d*2] = state->ExtReg[m*2];
} }
@ -884,13 +775,13 @@ void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
/* Miscellaneous functions */ /* Miscellaneous functions */
int32_t vfp_get_float(arm_core_t* state, unsigned int reg) int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
{ {
DEBUG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]); LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
return state->ExtReg[reg]; return state->ExtReg[reg];
} }
void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg) void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
{ {
DEBUG("VFP put float: s%d <= [%08x]\n", reg, val); LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
state->ExtReg[reg] = val; state->ExtReg[reg] = val;
} }
@ -898,13 +789,13 @@ uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
{ {
uint64_t result; uint64_t result;
result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2]; result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
DEBUG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result); LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
return result; return result;
} }
void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg) void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
{ {
DEBUG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff)); LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff); state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
state->ExtReg[reg*2+1] = (uint32_t) (val>>32); state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
} }
@ -916,10 +807,10 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
{ {
int si_code = 0; int si_code = 0;
vfpdebug("VFP: raising exceptions %08x\n", exceptions); LOG_DEBUG(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
if (exceptions == VFP_EXCEPTION_ERROR) { if (exceptions == VFP_EXCEPTION_ERROR) {
DEBUG("unhandled bounce %x\n", inst); LOG_TRACE(Core_ARM11, "unhandled bounce %x\n", inst);
exit(-1); exit(-1);
return; return;
} }

9
src/core/arm/skyeye_common/vfp/vfp.h
View File

@ -21,15 +21,10 @@
#ifndef __VFP_H__ #ifndef __VFP_H__
#define __VFP_H__ #define __VFP_H__
#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__)
#define vfpdebug //printf
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */ #include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
#define VFP_DEBUG_TRANSLATE DBG("in func %s, %x\n", __FUNCTION__, inst); #define VFP_DEBUG_UNIMPLEMENTED(x) LOG_ERROR(Core_ARM11, "in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
#define VFP_DEBUG_UNIMPLEMENTED(x) printf("in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1); #define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__);
#define VFP_DEBUG_UNTESTED(x) printf("in func %s, " #x " untested\n", __FUNCTION__);
#define CHECK_VFP_ENABLED #define CHECK_VFP_ENABLED
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);} #define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}

83
src/core/arm/skyeye_common/vfp/vfpdouble.cpp
View File

@ -63,7 +63,7 @@ static struct vfp_double vfp_double_default_qnan = {
static void vfp_double_dump(const char *str, struct vfp_double *d) static void vfp_double_dump(const char *str, struct vfp_double *d)
{ {
pr_debug("VFP: %s: sign=%d exponent=%d significand=%016llx\n", LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx\n",
str, d->sign != 0, d->exponent, d->significand); str, d->sign != 0, d->exponent, d->significand);
} }
@ -155,7 +155,7 @@ u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u
else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0)) else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1; incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
pr_debug("VFP: rounding increment = 0x%08llx\n", incr); LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
/* /*
* Is our rounding going to overflow? * Is our rounding going to overflow?
@ -281,7 +281,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
} else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0)) } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1; incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
pr_debug("VFP: rounding increment = 0x%08llx\n", incr); LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
/* /*
* Is our rounding going to overflow? * Is our rounding going to overflow?
@ -336,7 +336,7 @@ pack:
vfp_double_dump("pack: final", vd); vfp_double_dump("pack: final", vd);
{ {
s64 d = vfp_double_pack(vd); s64 d = vfp_double_pack(vd);
pr_debug("VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func, LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
dd, d, exceptions); dd, d, exceptions);
vfp_put_double(state, d, dd); vfp_put_double(state, d, dd);
} }
@ -393,28 +393,28 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn,
*/ */
static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd); vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
return 0; return 0;
} }
static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_get_double(state, dm), dd); vfp_put_double(state, vfp_get_double(state, dm), dd);
return 0; return 0;
} }
static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd); vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
return 0; return 0;
} }
static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double vdm, vdd, *vdp; vfp_double vdm, vdd, *vdp;
int ret, tm; int ret, tm;
@ -508,7 +508,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
s64 d, m; s64 d, m;
u32 ret = 0; u32 ret = 0;
pr_debug("In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr); LOG_TRACE(Core_ARM11, "In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
m = vfp_get_double(state, dm); m = vfp_get_double(state, dm);
if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) { if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
ret |= FPSCR_C | FPSCR_V; ret |= FPSCR_C | FPSCR_V;
@ -563,32 +563,32 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
ret |= FPSCR_C; ret |= FPSCR_C;
} }
} }
pr_debug("In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret); LOG_TRACE(Core_ARM11, "In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret);
return ret; return ret;
} }
static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 0, dm, fpscr); return vfp_compare(state, dd, 0, dm, fpscr);
} }
static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 1, dm, fpscr); return vfp_compare(state, dd, 1, dm, fpscr);
} }
static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr); return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
} }
static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr); return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
} }
@ -598,7 +598,7 @@ u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double*
int tm; int tm;
u32 exceptions = 0; u32 exceptions = 0;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
tm = vfp_double_type(dm); tm = vfp_double_type(dm);
@ -642,7 +642,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
int tm; int tm;
u32 exceptions = 0; u32 exceptions = 0;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm)); vfp_double_unpack(&vdm, vfp_get_double(state, dm));
tm = vfp_double_type(&vdm); tm = vfp_double_type(&vdm);
@ -684,7 +684,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm; struct vfp_double vdm;
u32 m = vfp_get_float(state, dm); u32 m = vfp_get_float(state, dm);
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vdm.sign = 0; vdm.sign = 0;
vdm.exponent = 1023 + 63 - 1; vdm.exponent = 1023 + 63 - 1;
vdm.significand = (u64)m; vdm.significand = (u64)m;
@ -697,7 +697,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm; struct vfp_double vdm;
u32 m = vfp_get_float(state, dm); u32 m = vfp_get_float(state, dm);
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vdm.sign = (m & 0x80000000) >> 16; vdm.sign = (m & 0x80000000) >> 16;
vdm.exponent = 1023 + 63 - 1; vdm.exponent = 1023 + 63 - 1;
vdm.significand = vdm.sign ? -m : m; vdm.significand = vdm.sign ? -m : m;
@ -712,7 +712,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK; int rmode = fpscr & FPSCR_RMODE_MASK;
int tm; int tm;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm)); vfp_double_unpack(&vdm, vfp_get_double(state, dm));
/* /*
@ -773,7 +773,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
} }
} }
pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
vfp_put_float(state, d, sd); vfp_put_float(state, d, sd);
@ -782,7 +782,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO); return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO);
} }
@ -793,7 +793,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK; int rmode = fpscr & FPSCR_RMODE_MASK;
int tm; int tm;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm)); vfp_double_unpack(&vdm, vfp_get_double(state, dm));
vfp_double_dump("VDM", &vdm); vfp_double_dump("VDM", &vdm);
@ -850,7 +850,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
} }
} }
pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
vfp_put_float(state, (s32)d, sd); vfp_put_float(state, (s32)d, sd);
@ -859,7 +859,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO); return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO);
} }
@ -894,9 +894,6 @@ static struct op fops_ext[] = {
{ vfp_double_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ { vfp_double_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ
}; };
static u32 static u32
vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn, vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn,
struct vfp_double *vdm, u32 fpscr) struct vfp_double *vdm, u32 fpscr)
@ -946,7 +943,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou
if (vdn->significand & (1ULL << 63) || if (vdn->significand & (1ULL << 63) ||
vdm->significand & (1ULL << 63)) { vdm->significand & (1ULL << 63)) {
pr_info("VFP: bad FP values in %s\n", __func__); LOG_INFO(Core_ARM11, "VFP: bad FP values in %s\n", __func__);
vfp_double_dump("VDN", vdn); vfp_double_dump("VDN", vdn);
vfp_double_dump("VDM", vdm); vfp_double_dump("VDM", vdm);
} }
@ -1018,7 +1015,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
struct vfp_double *t = vdn; struct vfp_double *t = vdn;
vdn = vdm; vdn = vdm;
vdm = t; vdm = t;
pr_debug("VFP: swapping M <-> N\n"); LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N\n");
} }
vdd->sign = vdn->sign ^ vdm->sign; vdd->sign = vdn->sign ^ vdm->sign;
@ -1099,7 +1096,7 @@ vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 f
*/ */
static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac"); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
} }
@ -1108,7 +1105,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/ */
static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac"); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
} }
@ -1117,7 +1114,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
*/ */
static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc"); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
} }
@ -1126,7 +1123,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/ */
static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{ {
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc"); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc");
} }
@ -1138,7 +1135,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm; struct vfp_double vdd, vdn, vdm;
u32 exceptions; u32 exceptions;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn)); vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand) if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn); vfp_double_normalise_denormal(&vdn);
@ -1159,7 +1156,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
struct vfp_double vdd, vdn, vdm; struct vfp_double vdd, vdn, vdm;
u32 exceptions; u32 exceptions;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn)); vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand) if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn); vfp_double_normalise_denormal(&vdn);
@ -1182,7 +1179,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm; struct vfp_double vdd, vdn, vdm;
u32 exceptions; u32 exceptions;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn)); vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand) if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn); vfp_double_normalise_denormal(&vdn);
@ -1204,7 +1201,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm; struct vfp_double vdd, vdn, vdm;
u32 exceptions; u32 exceptions;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn)); vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand) if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn); vfp_double_normalise_denormal(&vdn);
@ -1232,7 +1229,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
u32 exceptions = 0; u32 exceptions = 0;
int tm, tn; int tm, tn;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn)); vfp_double_unpack(&vdn, vfp_get_double(state, dn));
vfp_double_unpack(&vdm, vfp_get_double(state, dm)); vfp_double_unpack(&vdm, vfp_get_double(state, dm));
@ -1357,7 +1354,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
unsigned int vecitr, veclen, vecstride; unsigned int vecitr, veclen, vecstride;
struct op *fop; struct op *fop;
pr_debug("In %s\n", __FUNCTION__); LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)); vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
@ -1388,7 +1385,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
else else
veclen = fpscr & FPSCR_LENGTH_MASK; veclen = fpscr & FPSCR_LENGTH_MASK;
pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u\n", vecstride,
(veclen >> FPSCR_LENGTH_BIT) + 1); (veclen >> FPSCR_LENGTH_BIT) + 1);
if (!fop->fn) { if (!fop->fn) {
@ -1402,16 +1399,16 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
type = fop->flags & OP_SD ? 's' : 'd'; type = fop->flags & OP_SD ? 's' : 'd';
if (op == FOP_EXT) if (op == FOP_EXT)
pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n", LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT, vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, dm); type, dest, dn, dm);
else else
pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n", LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT, vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, FOP_TO_IDX(op), dm); type, dest, dn, FOP_TO_IDX(op), dm);
except = fop->fn(state, dest, dn, dm, fpscr); except = fop->fn(state, dest, dn, dm, fpscr);
pr_debug("VFP: itr%d: exceptions=%08x\n", LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x\n",
vecitr >> FPSCR_LENGTH_BIT, except); vecitr >> FPSCR_LENGTH_BIT, except);
exceptions |= except; exceptions |= except;

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src/core/arm/skyeye_common/vfp/vfpinstr.cpp
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