ARM: Merged additional ARMv6 instructions implemented by 3dmoo.
This commit is contained in:
bunnei
parent
bc6989b075
commit
0832cf7cd7
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@ -63,13 +63,6 @@ static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
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static void Handle_Load_Double (ARMul_State *, ARMword);
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static void Handle_Store_Double (ARMul_State *, ARMword);
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void
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XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far);
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int
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XScale_debug_moe (ARMul_State * state, int moe);
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unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
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unsigned cpnum);
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static int
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handle_v6_insn (ARMul_State * state, ARMword instr);
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@ -376,7 +369,7 @@ ARMul_Emulate26 (ARMul_State * state)
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#endif
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{
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/* The PC pipeline value depends on whether ARM
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or Thumb instructions are being
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or Thumb instructions are being
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d. */
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ARMword isize;
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ARMword instr; /* The current instruction. */
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@ -538,6 +531,7 @@ ARMul_Emulate26 (ARMul_State * state)
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state->AbortAddr = 1;
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instr = ARMul_LoadInstrN (state, pc, isize);
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//chy 2006-04-12, for ICE debug
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have_bp=ARMul_ICE_debug(state,instr,pc);
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#if 0
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@ -562,6 +556,7 @@ ARMul_Emulate26 (ARMul_State * state)
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}
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printf("\n");
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#endif
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instr = ARMul_LoadInstrN (state, pc, isize);
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state->last_instr = state->CurrInstr;
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state->CurrInstr = instr;
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@ -952,9 +947,8 @@ ARMul_Emulate26 (ARMul_State * state)
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case t_decoded:
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/* ARM instruction available. */
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//printf("t decode %04lx -> %08lx\n", instr & 0xffff, armOp);
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if (armOp == 0xDEADC0DE)
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{
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if (armOp == 0xDEADC0DE) {
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DEBUG("Failed to decode thumb opcode %04X at %08X\n", instr, pc);
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}
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@ -967,7 +961,6 @@ ARMul_Emulate26 (ARMul_State * state)
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}
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}
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#endif
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/* Check the condition codes. */
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if ((temp = TOPBITS (28)) == AL) {
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/* Vile deed in the need for speed. */
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@ -1124,6 +1117,7 @@ ARMul_Emulate26 (ARMul_State * state)
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//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
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/* Actual execution of instructions begins here. */
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/* If the condition codes don't match, stop here. */
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if (temp) {
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@ -2308,12 +2302,9 @@ mainswitch:
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if (state->Aborted) {
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TAKEABORT;
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}
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if (enter)
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{
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if (enter) {
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state->Reg[DESTReg] = 0;
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}
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else
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{
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} else {
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state->Reg[DESTReg] = 1;
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}
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break;
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@ -3063,7 +3054,27 @@ mainswitch:
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break;
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case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
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if (BIT (4)) {
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//ichfly PKHBT PKHTB todo check this
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if ((instr & 0x70) == 0x10) //pkhbt
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{
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u8 idest = BITS(12, 15);
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u8 rfis = BITS(16, 19);
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u8 rlast = BITS(0, 3);
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u8 ishi = BITS(7,11);
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state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
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break;
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}
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else if ((instr & 0x70) == 0x50)//pkhtb
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{
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u8 idest = BITS(12, 15);
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u8 rfis = BITS(16, 19);
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u8 rlast = BITS(0, 3);
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u8 ishi = BITS(7, 11);
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if (ishi == 0)ishi = 0x20;
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state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000);
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break;
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}
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else if (BIT (4)) {
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#ifdef MODE32
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if (state->is_v6
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&& handle_v6_insn (state, instr))
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@ -3675,7 +3686,13 @@ mainswitch:
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/* Co-Processor Data Transfers. */
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case 0xc4:
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if (state->is_v5) {
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if ((instr & 0x0FF00FF0) == 0xC400B10) //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
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{
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state->ExtReg[BITS(0, 3) << 1] = state->Reg[BITS(12, 15)];
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state->ExtReg[(BITS(0, 3) << 1) + 1] = state->Reg[BITS(16, 20)];
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break;
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}
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else if (state->is_v5) {
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/* Reading from R15 is UNPREDICTABLE. */
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if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
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ARMul_UndefInstr (state, instr);
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@ -3695,13 +3712,21 @@ mainswitch:
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break;
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case 0xc5:
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if (state->is_v5) {
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if ((instr & 0x00000FF0) == 0xB10) //vmov BIT(12-15), BIT(16-20), BIT(0-3) vmov r0, r0, d0
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{
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state->Reg[BITS(12, 15)] = state->ExtReg[BITS(0, 3) << 1];
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state->Reg[BITS(16, 19)] = state->ExtReg[(BITS(0, 3) << 1) + 1];
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break;
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}
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else if (state->is_v5) {
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/* Writes to R15 are UNPREDICATABLE. */
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if (DESTReg == 15 || LHSReg == 15)
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ARMul_UndefInstr (state, instr);
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/* Is access to the coprocessor allowed ? */
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else if (!CP_ACCESS_ALLOWED(state, CPNum))
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ARMul_UndefInstr (state, instr);
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{
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ARMul_UndefInstr(state, instr);
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}
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else {
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/* MRRC, ARMv5TE and up */
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ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg]));
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@ -4059,9 +4084,11 @@ TEST_EMULATE:
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// continue;
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else if (state->Emulate != RUN)
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break;
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}
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while (state->NumInstrsToExecute--);
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}
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while (state->NumInstrsToExecute);
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exit:
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state->decoded = decoded;
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state->loaded = loaded;
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state->pc = pc;
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@ -5686,12 +5713,98 @@ L_stm_s_takeabort:
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case 0x3f:
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printf ("Unhandled v6 insn: rbit\n");
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break;
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#endif
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case 0x61:
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printf ("Unhandled v6 insn: sadd/ssub\n");
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if ((instr & 0xFF0) == 0xf70)//ssub16
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = (a1 - a2)&0xFFFF | (((b1 - b2)&0xFFFF)<< 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf10)//sadd16
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = (a1 + a2)&0xFFFF | (((b1 + b2)&0xFFFF)<< 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf50)//ssax
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = (a1 - b2) & 0xFFFF | (((a2 + b1) & 0xFFFF) << 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf30)//sasx
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = (a2 - b1) & 0xFFFF | (((a2 + b1) & 0xFFFF) << 0x10);
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return 1;
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}
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else printf ("Unhandled v6 insn: sadd/ssub\n");
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break;
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case 0x62:
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printf ("Unhandled v6 insn: qadd/qsub\n");
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if ((instr & 0xFF0) == 0xf70)//QSUB16
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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s32 res1 = (a1 - b1);
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s32 res2 = (a2 - b2);
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if (res1 > 0x7FFF) res1 = 0x7FFF;
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if (res2 > 0x7FFF) res2 = 0x7FFF;
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if (res1 < 0x7FFF) res1 = -0x8000;
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if (res2 < 0x7FFF) res2 = -0x8000;
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state->Reg[tar] = (res1 & 0xFFFF) | ((res2 & 0xFFFF) << 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf10)//QADD16
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{
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = (state->Reg[src2] & 0xFFFF);
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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s32 res1 = (a1 + b1);
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s32 res2 = (a2 + b2);
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if (res1 > 0x7FFF) res1 = 0x7FFF;
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if (res2 > 0x7FFF) res2 = 0x7FFF;
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if (res1 < 0x7FFF) res1 = -0x8000;
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if (res2 < 0x7FFF) res2 = -0x8000;
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state->Reg[tar] = ((res1) & 0xFFFF) | (((res2) & 0xFFFF) << 0x10);
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return 1;
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}
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else printf ("Unhandled v6 insn: qadd/qsub\n");
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break;
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#if 0
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case 0x63:
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printf ("Unhandled v6 insn: shadd/shsub\n");
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break;
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@ -5709,10 +5822,65 @@ L_stm_s_takeabort:
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break;
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#endif
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case 0x6c:
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printf ("Unhandled v6 insn: uxtb16/uxtab16\n");
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if ((instr & 0xf03f0) == 0xf0070) //uxtb16
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{
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u8 src1 = BITS(0, 3);
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u8 tar = BITS(12, 15);
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u32 base = state->Reg[src1];
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u32 shamt = BITS(9,10)* 8;
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u32 in = ((base << (32 - shamt)) | (base >> shamt));
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state->Reg[tar] = in & 0x00FF00FF;
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return 1;
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}
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else
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printf ("Unhandled v6 insn: uxtb16/uxtab16\n");
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break;
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case 0x70:
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printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n");
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if ((instr & 0xf0d0) == 0xf010)//smuad //ichfly
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{
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u8 tar = BITS(16, 19);
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u8 src1 = BITS(0, 3);
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u8 src2 = BITS(8, 11);
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u8 swap = BIT(5);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
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s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = a1*a2 + b1*b2;
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return 1;
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}
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else if ((instr & 0xf0d0) == 0xf050)//smusd
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{
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u8 tar = BITS(16, 19);
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u8 src1 = BITS(0, 3);
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u8 src2 = BITS(8, 11);
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u8 swap = BIT(5);
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
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s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = a1*a2 - b1*b2;
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return 1;
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}
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else if ((instr & 0xd0) == 0x10)//smlad
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{
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u8 tar = BITS(16, 19);
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u8 src1 = BITS(0, 3);
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u8 src2 = BITS(8, 11);
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u8 src3 = BITS(12, 15);
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u8 swap = BIT(5);
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u32 a3 = state->Reg[src3];
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s16 a1 = (state->Reg[src1] & 0xFFFF);
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s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
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s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
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s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = a1*a2 + b1*b2 + a3;
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return 1;
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}
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else printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n");
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break;
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case 0x74:
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printf ("Unhandled v6 insn: smlald/smlsld\n");
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@ -5750,13 +5918,10 @@ L_stm_s_takeabort:
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if (state->Aborted) {
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TAKEABORT;
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}
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if (enter)
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{
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if (enter) {
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state->Reg[DESTReg] = 0;
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}
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else
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{
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} else {
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state->Reg[DESTReg] = 1;
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}
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@ -5795,12 +5960,9 @@ L_stm_s_takeabort:
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}
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if (enter)
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{
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if (enter) {
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state->Reg[DESTReg] = 0;
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}
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else
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{
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} else {
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state->Reg[DESTReg] = 1;
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}
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@ -5853,8 +6015,25 @@ L_stm_s_takeabort:
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case 0x01:
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case 0xf3:
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printf ("Unhandled v6 insn: ssat\n");
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return 0;
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//ichfly
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//SSAT16
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{
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u8 tar = BITS(12,15);
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u8 src = BITS(0, 3);
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u8 val = BITS(16, 19) + 1;
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s16 a1 = (state->Reg[src]);
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s16 a2 = (state->Reg[src] >> 0x10);
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s16 min = (s16)(0x8000) >> (16 - val);
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s16 max = 0x7FFF >> (16 - val);
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if (min > a1) a1 = min;
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if (max < a1) a1 = max;
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if (min > a2) a2 = min;
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if (max < a2) a2 = max;
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u32 temp2 = ((u32)(a2)) << 0x10;
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state->Reg[tar] = (a1&0xFFFF) | (temp2);
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}
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return 1;
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default:
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break;
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}
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@ -5944,8 +6123,21 @@ L_stm_s_takeabort:
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case 0x01:
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case 0xf3:
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printf ("Unhandled v6 insn: usat\n");
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return 0;
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//ichfly
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//USAT16
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{
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u8 tar = BITS(12, 15);
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u8 src = BITS(0, 3);
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u8 val = BITS(16, 19);
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s16 a1 = (state->Reg[src]);
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s16 a2 = (state->Reg[src] >> 0x10);
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s16 max = 0xFFFF >> (16 - val);
|
||||
if (max < a1) a1 = max;
|
||||
if (max < a2) a2 = max;
|
||||
u32 temp2 = ((u32)(a2)) << 0x10;
|
||||
state->Reg[tar] = (a1 & 0xFFFF) | (temp2);
|
||||
}
|
||||
return 1;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Reference in New Issue