NVDRV: Refactor Host1x
This commit is contained in:
parent
668e80a9f4
commit
2931101e6f
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@ -216,7 +216,7 @@ struct System::Impl {
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telemetry_session = std::make_unique<Core::TelemetrySession>();
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host1x_core = std::make_unique<Tegra::Host1x::Host1x>();
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host1x_core = std::make_unique<Tegra::Host1x::Host1x>(system);
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gpu_core = VideoCore::CreateGPU(emu_window, system);
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if (!gpu_core) {
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return SystemResultStatus::ErrorVideoCore;
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@ -6,18 +6,18 @@
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#include "core/hle/service/nvdrv/core/container.h"
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#include "core/hle/service/nvdrv/core/nvmap.h"
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#include "core/hle/service/nvdrv/core/syncpoint_manager.h"
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#include "video_core/gpu.h"
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#include "video_core/host1x/host1x.h"
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namespace Service::Nvidia::NvCore {
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struct ContainerImpl {
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ContainerImpl(Tegra::GPU& gpu_) : file{}, manager{gpu_} {}
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ContainerImpl(Tegra::Host1x::Host1x& host1x_) : file{host1x_}, manager{host1x_} {}
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NvMap file;
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SyncpointManager manager;
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};
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Container::Container(Tegra::GPU& gpu_) {
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impl = std::make_unique<ContainerImpl>(gpu_);
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Container::Container(Tegra::Host1x::Host1x& host1x_) {
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impl = std::make_unique<ContainerImpl>(host1x_);
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}
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Container::~Container() = default;
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@ -8,8 +8,12 @@
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#include <memory>
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namespace Tegra {
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class GPU;
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}
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namespace Host1x {
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class Host1x;
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} // namespace Host1x
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} // namespace Tegra
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namespace Service::Nvidia::NvCore {
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@ -20,7 +24,7 @@ struct ContainerImpl;
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class Container {
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public:
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Container(Tegra::GPU& gpu_);
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Container(Tegra::Host1x::Host1x& host1x);
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~Container();
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NvMap& GetNvMapFile();
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@ -7,6 +7,7 @@
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#include "common/logging/log.h"
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#include "core/hle/service/nvdrv/core/nvmap.h"
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#include "core/memory.h"
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#include "video_core/host1x/host1x.h"
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using Core::Memory::YUZU_PAGESIZE;
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@ -61,7 +62,7 @@ NvResult NvMap::Handle::Duplicate(bool internal_session) {
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return NvResult::Success;
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}
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NvMap::NvMap() = default;
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NvMap::NvMap(Tegra::Host1x::Host1x& host1x_) : host1x{host1x_} {}
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void NvMap::AddHandle(std::shared_ptr<Handle> handle_description) {
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std::scoped_lock lock(handles_lock);
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@ -77,12 +78,11 @@ void NvMap::UnmapHandle(Handle& handle_description) {
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}
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// Free and unmap the handle from the SMMU
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/*
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state.soc->smmu.Unmap(handle_description.pin_virt_address,
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static_cast<u32>(handle_description.aligned_size));
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smmuAllocator.Free(handle_description.pin_virt_address,
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static_cast<u32>(handle_description.aligned_size)); handle_description.pin_virt_address = 0;
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*/
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host1x.MemoryManager().Unmap(static_cast<GPUVAddr>(handle_description.pin_virt_address),
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handle_description.aligned_size);
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host1x.Allocator().Free(handle_description.pin_virt_address,
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static_cast<u32>(handle_description.aligned_size));
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handle_description.pin_virt_address = 0;
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}
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bool NvMap::TryRemoveHandle(const Handle& handle_description) {
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@ -131,12 +131,9 @@ VAddr NvMap::GetHandleAddress(Handle::Id handle) {
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}
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u32 NvMap::PinHandle(NvMap::Handle::Id handle) {
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UNIMPLEMENTED_MSG("pinning");
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return 0;
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/*
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auto handle_description{GetHandle(handle)};
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if (!handle_description)
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[[unlikely]] return 0;
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if (!handle_description) [[unlikely]]
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return 0;
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std::scoped_lock lock(handle_description->mutex);
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if (!handle_description->pins) {
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@ -157,8 +154,10 @@ u32 NvMap::PinHandle(NvMap::Handle::Id handle) {
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// If not then allocate some space and map it
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u32 address{};
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auto& smmu_allocator = host1x.Allocator();
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auto& smmu_memory_manager = host1x.MemoryManager();
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while (!(address =
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smmuAllocator.Allocate(static_cast<u32>(handle_description->aligned_size)))) {
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smmu_allocator.Allocate(static_cast<u32>(handle_description->aligned_size)))) {
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// Free handles until the allocation succeeds
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std::scoped_lock queueLock(unmap_queue_lock);
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if (auto freeHandleDesc{unmap_queue.front()}) {
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@ -172,19 +171,16 @@ u32 NvMap::PinHandle(NvMap::Handle::Id handle) {
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}
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}
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state.soc->smmu.Map(address, handle_description->GetPointer(),
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static_cast<u32>(handle_description->aligned_size));
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smmu_memory_manager.Map(static_cast<GPUVAddr>(address), handle_description->address,
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handle_description->aligned_size);
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handle_description->pin_virt_address = address;
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}
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handle_description->pins++;
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return handle_description->pin_virt_address;
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*/
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}
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void NvMap::UnpinHandle(Handle::Id handle) {
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UNIMPLEMENTED_MSG("Unpinning");
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/*
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auto handle_description{GetHandle(handle)};
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if (!handle_description)
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return;
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@ -199,7 +195,6 @@ void NvMap::UnpinHandle(Handle::Id handle) {
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unmap_queue.push_back(handle_description);
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handle_description->unmap_queue_entry = std::prev(unmap_queue.end());
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}
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*/
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}
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std::optional<NvMap::FreeInfo> NvMap::FreeHandle(Handle::Id handle, bool internal_session) {
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@ -15,6 +15,14 @@
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#include "common/common_types.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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namespace Tegra {
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namespace Host1x {
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class Host1x;
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} // namespace Host1x
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} // namespace Tegra
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namespace Service::Nvidia::NvCore {
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/**
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* @brief The nvmap core class holds the global state for nvmap and provides methods to manage
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@ -90,15 +98,17 @@ public:
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};
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private:
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std::list<std::shared_ptr<Handle>> unmap_queue;
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std::mutex unmap_queue_lock; //!< Protects access to `unmap_queue`
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std::list<std::shared_ptr<Handle>> unmap_queue{};
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std::mutex unmap_queue_lock{}; //!< Protects access to `unmap_queue`
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std::unordered_map<Handle::Id, std::shared_ptr<Handle>> handles; //!< Main owning map of handles
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std::unordered_map<Handle::Id, std::shared_ptr<Handle>>
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handles{}; //!< Main owning map of handles
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std::mutex handles_lock; //!< Protects access to `handles`
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static constexpr u32 HandleIdIncrement{
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4}; //!< Each new handle ID is an increment of 4 from the previous
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std::atomic<u32> next_handle_id{HandleIdIncrement};
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Tegra::Host1x::Host1x& host1x;
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void AddHandle(std::shared_ptr<Handle> handle);
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@ -125,7 +135,7 @@ public:
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bool was_uncached; //!< If the handle was allocated as uncached
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};
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NvMap();
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NvMap(Tegra::Host1x::Host1x& host1x);
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/**
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* @brief Creates an unallocated handle of the given size
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@ -3,16 +3,16 @@
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#include "common/assert.h"
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#include "core/hle/service/nvdrv/core/syncpoint_manager.h"
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#include "video_core/gpu.h"
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#include "video_core/host1x/host1x.h"
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namespace Service::Nvidia::NvCore {
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SyncpointManager::SyncpointManager(Tegra::GPU& gpu_) : gpu{gpu_} {}
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SyncpointManager::SyncpointManager(Tegra::Host1x::Host1x& host1x_) : host1x{host1x_} {}
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SyncpointManager::~SyncpointManager() = default;
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u32 SyncpointManager::RefreshSyncpoint(u32 syncpoint_id) {
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syncpoints[syncpoint_id].min = gpu.GetSyncpointValue(syncpoint_id);
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syncpoints[syncpoint_id].min = host1x.GetSyncpointManager().GetHostSyncpointValue(syncpoint_id);
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return GetSyncpointMin(syncpoint_id);
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}
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@ -10,14 +10,18 @@
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#include "core/hle/service/nvdrv/nvdata.h"
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namespace Tegra {
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class GPU;
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}
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namespace Host1x {
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class Host1x;
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} // namespace Host1x
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} // namespace Tegra
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namespace Service::Nvidia::NvCore {
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class SyncpointManager final {
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public:
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explicit SyncpointManager(Tegra::GPU& gpu_);
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explicit SyncpointManager(Tegra::Host1x::Host1x& host1x);
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~SyncpointManager();
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/**
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@ -78,7 +82,7 @@ private:
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std::array<Syncpoint, MaxSyncPoints> syncpoints{};
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Tegra::GPU& gpu;
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Tegra::Host1x::Host1x& host1x;
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};
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} // namespace Service::Nvidia::NvCore
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@ -13,6 +13,7 @@
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#include "core/hle/service/nvdrv/core/syncpoint_manager.h"
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#include "core/hle/service/nvdrv/devices/nvhost_nvdec_common.h"
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#include "core/memory.h"
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#include "video_core/host1x/host1x.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_base.h"
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@ -140,29 +141,8 @@ NvResult nvhost_nvdec_common::MapBuffer(const std::vector<u8>& input, std::vecto
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SliceVectors(input, cmd_buffer_handles, params.num_entries, sizeof(IoctlMapBuffer));
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auto& gpu = system.GPU();
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for (auto& cmd_buffer : cmd_buffer_handles) {
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auto object{nvmap.GetHandle(cmd_buffer.map_handle)};
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if (!object) {
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LOG_ERROR(Service_NVDRV, "invalid cmd_buffer nvmap_handle={:X}", cmd_buffer.map_handle);
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std::memcpy(output.data(), ¶ms, output.size());
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return NvResult::InvalidState;
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}
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if (object->dma_map_addr == 0) {
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// NVDEC and VIC memory is in the 32-bit address space
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// MapAllocate32 will attempt to map a lower 32-bit value in the shared gpu memory space
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const GPUVAddr low_addr =
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gpu.MemoryManager().MapAllocate32(object->address, object->size);
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object->dma_map_addr = static_cast<u32>(low_addr);
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// Ensure that the dma_map_addr is indeed in the lower 32-bit address space.
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ASSERT(object->dma_map_addr == low_addr);
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}
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if (!object->dma_map_addr) {
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LOG_ERROR(Service_NVDRV, "failed to map size={}", object->size);
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} else {
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cmd_buffer.map_address = static_cast<u32_le>(object->dma_map_addr);
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}
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cmd_buffer.map_address = nvmap.PinHandle(cmd_buffer.map_handle);
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}
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std::memcpy(output.data(), ¶ms, sizeof(IoctlMapBuffer));
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std::memcpy(output.data() + sizeof(IoctlMapBuffer), cmd_buffer_handles.data(),
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}
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NvResult nvhost_nvdec_common::UnmapBuffer(const std::vector<u8>& input, std::vector<u8>& output) {
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// This is intntionally stubbed.
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// Skip unmapping buffers here, as to not break the continuity of the VP9 reference frame
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// addresses, and risk invalidating data before the async GPU thread is done with it
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IoctlMapBuffer params{};
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std::memcpy(¶ms, input.data(), sizeof(IoctlMapBuffer));
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std::vector<MapBufferEntry> cmd_buffer_handles(params.num_entries);
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SliceVectors(input, cmd_buffer_handles, params.num_entries, sizeof(IoctlMapBuffer));
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for (auto& cmd_buffer : cmd_buffer_handles) {
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nvmap.UnpinHandle(cmd_buffer.map_handle);
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}
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std::memset(output.data(), 0, output.size());
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LOG_DEBUG(Service_NVDRV, "(STUBBED) called");
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return NvResult::Success;
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}
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@ -71,7 +71,7 @@ void InstallInterfaces(SM::ServiceManager& service_manager, NVFlinger::NVFlinger
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}
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Module::Module(Core::System& system)
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: service_context{system, "nvdrv"}, events_interface{*this}, container{system.GPU()} {
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: service_context{system, "nvdrv"}, events_interface{*this}, container{system.Host1x()} {
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builders["/dev/nvhost-as-gpu"] = [this, &system](DeviceFD fd) {
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std::shared_ptr<Devices::nvdevice> device =
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std::make_shared<Devices::nvhost_as_gpu>(system, *this, container);
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@ -56,6 +56,8 @@ add_library(video_core STATIC
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host1x/codecs/vp9_types.h
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host1x/control.cpp
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host1x/control.h
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host1x/host1x.cpp
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host1x/host1x.h
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host1x/nvdec.cpp
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host1x/nvdec.h
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host1x/nvdec_common.h
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@ -4,8 +4,8 @@
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#include <bit>
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#include "video_core/cdma_pusher.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/gpu.h"
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#include "video_core/host1x/control.h"
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#include "video_core/host1x/host1x.h"
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#include "video_core/host1x/nvdec.h"
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#include "video_core/host1x/nvdec_common.h"
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#include "video_core/host1x/sync_manager.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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CDmaPusher::CDmaPusher(GPU& gpu_)
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: gpu{gpu_}, nvdec_processor(std::make_shared<Host1x::Nvdec>(gpu)),
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vic_processor(std::make_unique<Host1x::Vic>(gpu, nvdec_processor)),
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host1x_processor(std::make_unique<Host1x::Control>(gpu)),
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sync_manager(std::make_unique<Host1x::SyncptIncrManager>(gpu)) {}
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CDmaPusher::CDmaPusher(Host1x::Host1x& host1x_)
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: host1x{host1x_}, nvdec_processor(std::make_shared<Host1x::Nvdec>(host1x)),
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vic_processor(std::make_unique<Host1x::Vic>(host1x, nvdec_processor)),
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host1x_processor(std::make_unique<Host1x::Control>(host1x)),
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sync_manager(std::make_unique<Host1x::SyncptIncrManager>(host1x)) {}
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CDmaPusher::~CDmaPusher() = default;
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namespace Tegra {
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class GPU;
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namespace Host1x {
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class Control;
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class Host1x;
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class Nvdec;
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class SyncptIncrManager;
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class Vic;
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@ -91,7 +90,7 @@ enum class ThiMethod : u32 {
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class CDmaPusher {
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public:
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explicit CDmaPusher(GPU& gpu_);
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explicit CDmaPusher(Host1x::Host1x& host1x);
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~CDmaPusher();
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/// Process the command entry
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/// Write arguments value to the ThiRegisters member at the specified offset
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void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument);
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GPU& gpu;
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Host1x::Host1x& host1x;
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std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor;
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std::unique_ptr<Tegra::Host1x::Vic> vic_processor;
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std::unique_ptr<Tegra::Host1x::Control> host1x_processor;
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@ -83,19 +83,11 @@ struct GPU::Impl {
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UNIMPLEMENTED();
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}
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void CreateHost1xChannel() {
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if (host1x_channel) {
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return;
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}
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host1x_channel = CreateChannel(0);
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host1x_channel->memory_manager = std::make_shared<Tegra::MemoryManager>(system);
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InitChannel(*host1x_channel);
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}
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
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renderer = std::move(renderer_);
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rasterizer = renderer->ReadRasterizer();
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host1x.MemoryManager().BindRasterizer(rasterizer);
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}
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/// Flush all current written commands into the host GPU for execution.
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@ -173,12 +165,6 @@ struct GPU::Impl {
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return *current_channel->kepler_compute;
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}
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/// Returns a reference to the GPU memory manager.
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[[nodiscard]] Tegra::MemoryManager& MemoryManager() {
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CreateHost1xChannel();
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return *host1x_channel->memory_manager;
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}
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher() {
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ASSERT(current_channel);
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@ -299,7 +285,7 @@ struct GPU::Impl {
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}
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if (!cdma_pushers.contains(id)) {
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cdma_pushers.insert_or_assign(id, std::make_unique<Tegra::CDmaPusher>(gpu));
|
||||
cdma_pushers.insert_or_assign(id, std::make_unique<Tegra::CDmaPusher>(host1x));
|
||||
}
|
||||
|
||||
// SubmitCommandBuffer would make the nvdec operations async, this is not currently working
|
||||
|
@ -389,7 +375,6 @@ struct GPU::Impl {
|
|||
VideoCore::RasterizerInterface* rasterizer = nullptr;
|
||||
const bool use_nvdec;
|
||||
|
||||
std::shared_ptr<Control::ChannelState> host1x_channel;
|
||||
s32 new_channel_id{1};
|
||||
/// Shader build notifier
|
||||
std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
|
||||
|
@ -510,14 +495,6 @@ const Engines::KeplerCompute& GPU::KeplerCompute() const {
|
|||
return impl->KeplerCompute();
|
||||
}
|
||||
|
||||
Tegra::MemoryManager& GPU::MemoryManager() {
|
||||
return impl->MemoryManager();
|
||||
}
|
||||
|
||||
const Tegra::MemoryManager& GPU::MemoryManager() const {
|
||||
return impl->MemoryManager();
|
||||
}
|
||||
|
||||
Tegra::DmaPusher& GPU::DmaPusher() {
|
||||
return impl->DmaPusher();
|
||||
}
|
||||
|
|
|
@ -153,12 +153,6 @@ public:
|
|||
/// Returns a reference to the KeplerCompute GPU engine.
|
||||
[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const;
|
||||
|
||||
/// Returns a reference to the GPU memory manager.
|
||||
[[nodiscard]] Tegra::MemoryManager& MemoryManager();
|
||||
|
||||
/// Returns a const reference to the GPU memory manager.
|
||||
[[nodiscard]] const Tegra::MemoryManager& MemoryManager() const;
|
||||
|
||||
/// Returns a reference to the GPU DMA pusher.
|
||||
[[nodiscard]] Tegra::DmaPusher& DmaPusher();
|
||||
|
||||
|
|
|
@ -6,11 +6,11 @@
|
|||
#include <vector>
|
||||
#include "common/assert.h"
|
||||
#include "common/settings.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/codecs/codec.h"
|
||||
#include "video_core/host1x/codecs/h264.h"
|
||||
#include "video_core/host1x/codecs/vp8.h"
|
||||
#include "video_core/host1x/codecs/vp9.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
||||
extern "C" {
|
||||
|
@ -73,10 +73,10 @@ void AVFrameDeleter(AVFrame* ptr) {
|
|||
av_frame_free(&ptr);
|
||||
}
|
||||
|
||||
Codec::Codec(GPU& gpu_, const Host1x::NvdecCommon::NvdecRegisters& regs)
|
||||
: gpu(gpu_), state{regs}, h264_decoder(std::make_unique<Decoder::H264>(gpu)),
|
||||
vp8_decoder(std::make_unique<Decoder::VP8>(gpu)),
|
||||
vp9_decoder(std::make_unique<Decoder::VP9>(gpu)) {}
|
||||
Codec::Codec(Host1x::Host1x& host1x_, const Host1x::NvdecCommon::NvdecRegisters& regs)
|
||||
: host1x(host1x_), state{regs}, h264_decoder(std::make_unique<Decoder::H264>(host1x)),
|
||||
vp8_decoder(std::make_unique<Decoder::VP8>(host1x)),
|
||||
vp9_decoder(std::make_unique<Decoder::VP9>(host1x)) {}
|
||||
|
||||
Codec::~Codec() {
|
||||
if (!initialized) {
|
||||
|
|
|
@ -21,7 +21,6 @@ extern "C" {
|
|||
}
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
void AVFrameDeleter(AVFrame* ptr);
|
||||
using AVFramePtr = std::unique_ptr<AVFrame, decltype(&AVFrameDeleter)>;
|
||||
|
@ -32,9 +31,13 @@ class VP8;
|
|||
class VP9;
|
||||
} // namespace Decoder
|
||||
|
||||
namespace Host1x {
|
||||
class Host1x;
|
||||
} // namespace Host1x
|
||||
|
||||
class Codec {
|
||||
public:
|
||||
explicit Codec(GPU& gpu, const Host1x::NvdecCommon::NvdecRegisters& regs);
|
||||
explicit Codec(Host1x::Host1x& host1x, const Host1x::NvdecCommon::NvdecRegisters& regs);
|
||||
~Codec();
|
||||
|
||||
/// Initialize the codec, returning success or failure
|
||||
|
@ -69,7 +72,7 @@ private:
|
|||
AVCodecContext* av_codec_ctx{nullptr};
|
||||
AVBufferRef* av_gpu_decoder{nullptr};
|
||||
|
||||
GPU& gpu;
|
||||
Host1x::Host1x& host1x;
|
||||
const Host1x::NvdecCommon::NvdecRegisters& state;
|
||||
std::unique_ptr<Decoder::H264> h264_decoder;
|
||||
std::unique_ptr<Decoder::VP8> vp8_decoder;
|
||||
|
|
|
@ -5,8 +5,8 @@
|
|||
#include <bit>
|
||||
|
||||
#include "common/settings.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/codecs/h264.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
||||
namespace Tegra::Decoder {
|
||||
|
@ -24,19 +24,20 @@ constexpr std::array<u8, 16> zig_zag_scan{
|
|||
};
|
||||
} // Anonymous namespace
|
||||
|
||||
H264::H264(GPU& gpu_) : gpu(gpu_) {}
|
||||
H264::H264(Host1x::Host1x& host1x_) : host1x{host1x_} {}
|
||||
|
||||
H264::~H264() = default;
|
||||
|
||||
const std::vector<u8>& H264::ComposeFrame(const Host1x::NvdecCommon::NvdecRegisters& state,
|
||||
bool is_first_frame) {
|
||||
H264DecoderContext context;
|
||||
gpu.MemoryManager().ReadBlock(state.picture_info_offset, &context, sizeof(H264DecoderContext));
|
||||
host1x.MemoryManager().ReadBlock(state.picture_info_offset, &context,
|
||||
sizeof(H264DecoderContext));
|
||||
|
||||
const s64 frame_number = context.h264_parameter_set.frame_number.Value();
|
||||
if (!is_first_frame && frame_number != 0) {
|
||||
frame.resize(context.stream_len);
|
||||
gpu.MemoryManager().ReadBlock(state.frame_bitstream_offset, frame.data(), frame.size());
|
||||
host1x.MemoryManager().ReadBlock(state.frame_bitstream_offset, frame.data(), frame.size());
|
||||
return frame;
|
||||
}
|
||||
|
||||
|
@ -155,8 +156,8 @@ const std::vector<u8>& H264::ComposeFrame(const Host1x::NvdecCommon::NvdecRegist
|
|||
frame.resize(encoded_header.size() + context.stream_len);
|
||||
std::memcpy(frame.data(), encoded_header.data(), encoded_header.size());
|
||||
|
||||
gpu.MemoryManager().ReadBlock(state.frame_bitstream_offset,
|
||||
frame.data() + encoded_header.size(), context.stream_len);
|
||||
host1x.MemoryManager().ReadBlock(state.frame_bitstream_offset,
|
||||
frame.data() + encoded_header.size(), context.stream_len);
|
||||
|
||||
return frame;
|
||||
}
|
||||
|
|
|
@ -11,7 +11,11 @@
|
|||
#include "video_core/host1x/nvdec_common.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
class Host1x;
|
||||
} // namespace Host1x
|
||||
|
||||
namespace Decoder {
|
||||
|
||||
class H264BitWriter {
|
||||
|
@ -55,7 +59,7 @@ private:
|
|||
|
||||
class H264 {
|
||||
public:
|
||||
explicit H264(GPU& gpu);
|
||||
explicit H264(Host1x::Host1x& host1x);
|
||||
~H264();
|
||||
|
||||
/// Compose the H264 frame for FFmpeg decoding
|
||||
|
@ -64,7 +68,7 @@ public:
|
|||
|
||||
private:
|
||||
std::vector<u8> frame;
|
||||
GPU& gpu;
|
||||
Host1x::Host1x& host1x;
|
||||
|
||||
struct H264ParameterSet {
|
||||
s32 log2_max_pic_order_cnt_lsb_minus4; ///< 0x00
|
||||
|
|
|
@ -3,18 +3,18 @@
|
|||
|
||||
#include <vector>
|
||||
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/codecs/vp8.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
||||
namespace Tegra::Decoder {
|
||||
VP8::VP8(GPU& gpu_) : gpu(gpu_) {}
|
||||
VP8::VP8(Host1x::Host1x& host1x_) : host1x{host1x_} {}
|
||||
|
||||
VP8::~VP8() = default;
|
||||
|
||||
const std::vector<u8>& VP8::ComposeFrame(const Host1x::NvdecCommon::NvdecRegisters& state) {
|
||||
VP8PictureInfo info;
|
||||
gpu.MemoryManager().ReadBlock(state.picture_info_offset, &info, sizeof(VP8PictureInfo));
|
||||
host1x.MemoryManager().ReadBlock(state.picture_info_offset, &info, sizeof(VP8PictureInfo));
|
||||
|
||||
const bool is_key_frame = info.key_frame == 1u;
|
||||
const auto bitstream_size = static_cast<size_t>(info.vld_buffer_size);
|
||||
|
@ -45,7 +45,7 @@ const std::vector<u8>& VP8::ComposeFrame(const Host1x::NvdecCommon::NvdecRegiste
|
|||
frame[9] = static_cast<u8>(((info.frame_height >> 8) & 0x3f));
|
||||
}
|
||||
const u64 bitstream_offset = state.frame_bitstream_offset;
|
||||
gpu.MemoryManager().ReadBlock(bitstream_offset, frame.data() + header_size, bitstream_size);
|
||||
host1x.MemoryManager().ReadBlock(bitstream_offset, frame.data() + header_size, bitstream_size);
|
||||
|
||||
return frame;
|
||||
}
|
||||
|
|
|
@ -11,12 +11,16 @@
|
|||
#include "video_core/host1x/nvdec_common.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
class Host1x;
|
||||
} // namespace Host1x
|
||||
|
||||
namespace Decoder {
|
||||
|
||||
class VP8 {
|
||||
public:
|
||||
explicit VP8(GPU& gpu);
|
||||
explicit VP8(Host1x::Host1x& host1x);
|
||||
~VP8();
|
||||
|
||||
/// Compose the VP8 frame for FFmpeg decoding
|
||||
|
@ -25,7 +29,7 @@ public:
|
|||
|
||||
private:
|
||||
std::vector<u8> frame;
|
||||
GPU& gpu;
|
||||
Host1x::Host1x& host1x;
|
||||
|
||||
struct VP8PictureInfo {
|
||||
INSERT_PADDING_WORDS_NOINIT(14);
|
||||
|
|
|
@ -4,8 +4,8 @@
|
|||
#include <algorithm> // for std::copy
|
||||
#include <numeric>
|
||||
#include "common/assert.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/codecs/vp9.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
||||
namespace Tegra::Decoder {
|
||||
|
@ -236,7 +236,7 @@ constexpr std::array<u8, 254> map_lut{
|
|||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
VP9::VP9(GPU& gpu_) : gpu{gpu_} {}
|
||||
VP9::VP9(Host1x::Host1x& host1x_) : host1x{host1x_} {}
|
||||
|
||||
VP9::~VP9() = default;
|
||||
|
||||
|
@ -357,7 +357,7 @@ void VP9::WriteMvProbabilityUpdate(VpxRangeEncoder& writer, u8 new_prob, u8 old_
|
|||
|
||||
Vp9PictureInfo VP9::GetVp9PictureInfo(const Host1x::NvdecCommon::NvdecRegisters& state) {
|
||||
PictureInfo picture_info;
|
||||
gpu.MemoryManager().ReadBlock(state.picture_info_offset, &picture_info, sizeof(PictureInfo));
|
||||
host1x.MemoryManager().ReadBlock(state.picture_info_offset, &picture_info, sizeof(PictureInfo));
|
||||
Vp9PictureInfo vp9_info = picture_info.Convert();
|
||||
|
||||
InsertEntropy(state.vp9_entropy_probs_offset, vp9_info.entropy);
|
||||
|
@ -372,17 +372,17 @@ Vp9PictureInfo VP9::GetVp9PictureInfo(const Host1x::NvdecCommon::NvdecRegisters&
|
|||
|
||||
void VP9::InsertEntropy(u64 offset, Vp9EntropyProbs& dst) {
|
||||
EntropyProbs entropy;
|
||||
gpu.MemoryManager().ReadBlock(offset, &entropy, sizeof(EntropyProbs));
|
||||
host1x.MemoryManager().ReadBlock(offset, &entropy, sizeof(EntropyProbs));
|
||||
entropy.Convert(dst);
|
||||
}
|
||||
|
||||
Vp9FrameContainer VP9::GetCurrentFrame(const Host1x::NvdecCommon::NvdecRegisters& state) {
|
||||
Vp9FrameContainer current_frame{};
|
||||
{
|
||||
gpu.SyncGuestHost();
|
||||
// gpu.SyncGuestHost(); epic, why?
|
||||
current_frame.info = GetVp9PictureInfo(state);
|
||||
current_frame.bit_stream.resize(current_frame.info.bitstream_size);
|
||||
gpu.MemoryManager().ReadBlock(state.frame_bitstream_offset, current_frame.bit_stream.data(),
|
||||
host1x.MemoryManager().ReadBlock(state.frame_bitstream_offset, current_frame.bit_stream.data(),
|
||||
current_frame.info.bitstream_size);
|
||||
}
|
||||
if (!next_frame.bit_stream.empty()) {
|
||||
|
|
|
@ -12,7 +12,11 @@
|
|||
#include "video_core/host1x/nvdec_common.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
class Host1x;
|
||||
} // namespace Host1x
|
||||
|
||||
namespace Decoder {
|
||||
|
||||
/// The VpxRangeEncoder, and VpxBitStreamWriter classes are used to compose the
|
||||
|
@ -106,7 +110,7 @@ private:
|
|||
|
||||
class VP9 {
|
||||
public:
|
||||
explicit VP9(GPU& gpu_);
|
||||
explicit VP9(Host1x::Host1x& host1x);
|
||||
~VP9();
|
||||
|
||||
VP9(const VP9&) = delete;
|
||||
|
@ -176,7 +180,7 @@ private:
|
|||
[[nodiscard]] std::vector<u8> ComposeCompressedHeader();
|
||||
[[nodiscard]] VpxBitStreamWriter ComposeUncompressedHeader();
|
||||
|
||||
GPU& gpu;
|
||||
Host1x::Host1x& host1x;
|
||||
std::vector<u8> frame;
|
||||
|
||||
std::array<s8, 4> loop_filter_ref_deltas{};
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Decoder {
|
||||
struct Vp9FrameDimensions {
|
||||
|
|
|
@ -3,13 +3,12 @@
|
|||
// Refer to the license.txt file included.
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/control.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
|
||||
namespace Tegra::Host1x {
|
||||
|
||||
Control::Control(GPU& gpu_) : gpu(gpu_) {}
|
||||
Control::Control(Host1x& host1x_) : host1x(host1x_) {}
|
||||
|
||||
Control::~Control() = default;
|
||||
|
||||
|
@ -29,7 +28,7 @@ void Control::ProcessMethod(Method method, u32 argument) {
|
|||
}
|
||||
|
||||
void Control::Execute(u32 data) {
|
||||
gpu.Host1x().GetSyncpointManager().WaitHost(data, syncpoint_value);
|
||||
host1x.GetSyncpointManager().WaitHost(data, syncpoint_value);
|
||||
}
|
||||
|
||||
} // namespace Tegra::Host1x
|
||||
|
|
|
@ -8,10 +8,10 @@
|
|||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
|
||||
class Host1x;
|
||||
class Nvdec;
|
||||
|
||||
class Control {
|
||||
|
@ -22,7 +22,7 @@ public:
|
|||
WaitSyncpt32 = 0x50,
|
||||
};
|
||||
|
||||
explicit Control(GPU& gpu);
|
||||
explicit Control(Host1x& host1x);
|
||||
~Control();
|
||||
|
||||
/// Writes the method into the state, Invoke Execute() if encountered
|
||||
|
@ -33,7 +33,7 @@ private:
|
|||
void Execute(u32 data);
|
||||
|
||||
u32 syncpoint_value{};
|
||||
GPU& gpu;
|
||||
Host1x& host1x;
|
||||
};
|
||||
|
||||
} // namespace Host1x
|
||||
|
|
|
@ -0,0 +1,18 @@
|
|||
// Copyright 2022 yuzu Emulator Project
|
||||
// Licensed under GPLv3 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "core/core.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Host1x {
|
||||
|
||||
Host1x::Host1x(Core::System& system_)
|
||||
: system{system_}, syncpoint_manager{}, memory_manager{system, 32, 12},
|
||||
allocator{std::make_unique<Common::FlatAllocator<u32, 0, 32>>(1 << 12)} {}
|
||||
|
||||
} // namespace Host1x
|
||||
|
||||
} // namespace Tegra
|
|
@ -6,7 +6,13 @@
|
|||
|
||||
#include "common/common_types.h"
|
||||
|
||||
#include "common/address_space.h"
|
||||
#include "video_core/host1x/syncpoint_manager.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
||||
namespace Core {
|
||||
class System;
|
||||
} // namespace Core
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
|
@ -14,7 +20,7 @@ namespace Host1x {
|
|||
|
||||
class Host1x {
|
||||
public:
|
||||
Host1x() : syncpoint_manager{} {}
|
||||
Host1x(Core::System& system);
|
||||
|
||||
SyncpointManager& GetSyncpointManager() {
|
||||
return syncpoint_manager;
|
||||
|
@ -24,8 +30,27 @@ public:
|
|||
return syncpoint_manager;
|
||||
}
|
||||
|
||||
Tegra::MemoryManager& MemoryManager() {
|
||||
return memory_manager;
|
||||
}
|
||||
|
||||
const Tegra::MemoryManager& MemoryManager() const {
|
||||
return memory_manager;
|
||||
}
|
||||
|
||||
Common::FlatAllocator<u32, 0, 32>& Allocator() {
|
||||
return *allocator;
|
||||
}
|
||||
|
||||
const Common::FlatAllocator<u32, 0, 32>& Allocator() const {
|
||||
return *allocator;
|
||||
}
|
||||
|
||||
private:
|
||||
Core::System& system;
|
||||
SyncpointManager syncpoint_manager;
|
||||
Tegra::MemoryManager memory_manager;
|
||||
std::unique_ptr<Common::FlatAllocator<u32, 0, 32>> allocator;
|
||||
};
|
||||
|
||||
} // namespace Host1x
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/host1x/nvdec.h"
|
||||
|
||||
namespace Tegra::Host1x {
|
||||
|
@ -10,7 +10,8 @@ namespace Tegra::Host1x {
|
|||
#define NVDEC_REG_INDEX(field_name) \
|
||||
(offsetof(NvdecCommon::NvdecRegisters, field_name) / sizeof(u64))
|
||||
|
||||
Nvdec::Nvdec(GPU& gpu_) : gpu(gpu_), state{}, codec(std::make_unique<Codec>(gpu, state)) {}
|
||||
Nvdec::Nvdec(Host1x& host1x_)
|
||||
: host1x(host1x_), state{}, codec(std::make_unique<Codec>(host1x, state)) {}
|
||||
|
||||
Nvdec::~Nvdec() = default;
|
||||
|
||||
|
|
|
@ -9,13 +9,14 @@
|
|||
#include "video_core/host1x/codecs/codec.h"
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
|
||||
class Host1x;
|
||||
|
||||
class Nvdec {
|
||||
public:
|
||||
explicit Nvdec(GPU& gpu);
|
||||
explicit Nvdec(Host1x& host1x);
|
||||
~Nvdec();
|
||||
|
||||
/// Writes the method into the state, Invoke Execute() if encountered
|
||||
|
@ -28,7 +29,7 @@ private:
|
|||
/// Invoke codec to decode a frame
|
||||
void Execute();
|
||||
|
||||
GPU& gpu;
|
||||
Host1x& host1x;
|
||||
NvdecCommon::NvdecRegisters state;
|
||||
std::unique_ptr<Codec> codec;
|
||||
};
|
||||
|
|
|
@ -3,14 +3,13 @@
|
|||
|
||||
#include <algorithm>
|
||||
#include "sync_manager.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/host1x/syncpoint_manager.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace Host1x {
|
||||
|
||||
SyncptIncrManager::SyncptIncrManager(GPU& gpu_) : gpu(gpu_) {}
|
||||
SyncptIncrManager::SyncptIncrManager(Host1x& host1x_) : host1x(host1x_) {}
|
||||
SyncptIncrManager::~SyncptIncrManager() = default;
|
||||
|
||||
void SyncptIncrManager::Increment(u32 id) {
|
||||
|
@ -40,7 +39,7 @@ void SyncptIncrManager::IncrementAllDone() {
|
|||
if (!increments[done_count].complete) {
|
||||
break;
|
||||
}
|
||||
auto& syncpoint_manager = gpu.Host1x().GetSyncpointManager();
|
||||
auto& syncpoint_manager = host1x.GetSyncpointManager();
|
||||
syncpoint_manager.IncrementGuest(increments[done_count].syncpt_id);
|
||||
syncpoint_manager.IncrementHost(increments[done_count].syncpt_id);
|
||||
}
|
||||
|
|
|
@ -9,10 +9,10 @@
|
|||
|
||||
namespace Tegra {
|
||||
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
|
||||
class Host1x;
|
||||
|
||||
struct SyncptIncr {
|
||||
u32 id;
|
||||
u32 class_id;
|
||||
|
@ -25,7 +25,7 @@ struct SyncptIncr {
|
|||
|
||||
class SyncptIncrManager {
|
||||
public:
|
||||
explicit SyncptIncrManager(GPU& gpu);
|
||||
explicit SyncptIncrManager(Host1x& host1x);
|
||||
~SyncptIncrManager();
|
||||
|
||||
/// Add syncpoint id and increment all
|
||||
|
@ -45,7 +45,7 @@ private:
|
|||
std::mutex increment_lock;
|
||||
u32 current_id{};
|
||||
|
||||
GPU& gpu;
|
||||
Host1x& host1x;
|
||||
};
|
||||
|
||||
} // namespace Host1x
|
||||
|
|
|
@ -19,7 +19,7 @@ extern "C" {
|
|||
#include "common/logging/log.h"
|
||||
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/host1x/host1x.h"
|
||||
#include "video_core/host1x/nvdec.h"
|
||||
#include "video_core/host1x/vic.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
|
@ -49,8 +49,8 @@ union VicConfig {
|
|||
BitField<46, 14, u64_le> surface_height_minus1;
|
||||
};
|
||||
|
||||
Vic::Vic(GPU& gpu_, std::shared_ptr<Nvdec> nvdec_processor_)
|
||||
: gpu(gpu_),
|
||||
Vic::Vic(Host1x& host1x_, std::shared_ptr<Nvdec> nvdec_processor_)
|
||||
: host1x(host1x_),
|
||||
nvdec_processor(std::move(nvdec_processor_)), converted_frame_buffer{nullptr, av_free} {}
|
||||
|
||||
Vic::~Vic() = default;
|
||||
|
@ -81,7 +81,7 @@ void Vic::Execute() {
|
|||
LOG_ERROR(Service_NVDRV, "VIC Luma address not set.");
|
||||
return;
|
||||
}
|
||||
const VicConfig config{gpu.MemoryManager().Read<u64>(config_struct_address + 0x20)};
|
||||
const VicConfig config{host1x.MemoryManager().Read<u64>(config_struct_address + 0x20)};
|
||||
const AVFramePtr frame_ptr = nvdec_processor->GetFrame();
|
||||
const auto* frame = frame_ptr.get();
|
||||
if (!frame) {
|
||||
|
@ -159,12 +159,12 @@ void Vic::WriteRGBFrame(const AVFrame* frame, const VicConfig& config) {
|
|||
Texture::SwizzleSubrect(width, height, width * 4, width, 4, luma_buffer.data(),
|
||||
converted_frame_buf_addr, block_height, 0, 0);
|
||||
|
||||
gpu.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(), size);
|
||||
host1x.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(), size);
|
||||
} else {
|
||||
// send pitch linear frame
|
||||
const size_t linear_size = width * height * 4;
|
||||
gpu.MemoryManager().WriteBlock(output_surface_luma_address, converted_frame_buf_addr,
|
||||
linear_size);
|
||||
host1x.MemoryManager().WriteBlock(output_surface_luma_address, converted_frame_buf_addr,
|
||||
linear_size);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -192,8 +192,8 @@ void Vic::WriteYUVFrame(const AVFrame* frame, const VicConfig& config) {
|
|||
luma_buffer[dst + x] = luma_src[src + x];
|
||||
}
|
||||
}
|
||||
gpu.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(),
|
||||
luma_buffer.size());
|
||||
host1x.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(),
|
||||
luma_buffer.size());
|
||||
|
||||
// Chroma
|
||||
const std::size_t half_height = frame_height / 2;
|
||||
|
@ -234,8 +234,8 @@ void Vic::WriteYUVFrame(const AVFrame* frame, const VicConfig& config) {
|
|||
ASSERT(false);
|
||||
break;
|
||||
}
|
||||
gpu.MemoryManager().WriteBlock(output_surface_chroma_address, chroma_buffer.data(),
|
||||
chroma_buffer.size());
|
||||
host1x.MemoryManager().WriteBlock(output_surface_chroma_address, chroma_buffer.data(),
|
||||
chroma_buffer.size());
|
||||
}
|
||||
|
||||
} // namespace Host1x
|
||||
|
|
|
@ -10,10 +10,10 @@
|
|||
struct SwsContext;
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
|
||||
namespace Host1x {
|
||||
|
||||
class Host1x;
|
||||
class Nvdec;
|
||||
union VicConfig;
|
||||
|
||||
|
@ -28,7 +28,7 @@ public:
|
|||
SetOutputSurfaceChromaUnusedOffset = 0x1ca
|
||||
};
|
||||
|
||||
explicit Vic(GPU& gpu, std::shared_ptr<Nvdec> nvdec_processor);
|
||||
explicit Vic(Host1x& host1x, std::shared_ptr<Nvdec> nvdec_processor);
|
||||
|
||||
~Vic();
|
||||
|
||||
|
@ -42,7 +42,7 @@ private:
|
|||
|
||||
void WriteYUVFrame(const AVFrame* frame, const VicConfig& config);
|
||||
|
||||
GPU& gpu;
|
||||
Host1x& host1x;
|
||||
std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor;
|
||||
|
||||
/// Avoid reallocation of the following buffers every frame, as their
|
||||
|
|
Reference in New Issue