dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
This commit is contained in:
parent
e8b9731af3
commit
32d127ad3e
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@ -1 +1 @@
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Subproject commit e585e1d49ed65c31edd567510e00508d42decb1c
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Subproject commit 6b4c6b06a94290690d2132adfa45a8087958c2c7
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@ -67,8 +67,17 @@ public:
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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ASSERT_MSG(false, "ExceptionRaised(exception = %zu, pc = %" PRIx64 ")",
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static_cast<size_t>(exception), pc);
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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default:
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ASSERT_MSG(false, "ExceptionRaised(exception = %zu, pc = %" PRIx64 ")",
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static_cast<size_t>(exception), pc);
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}
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}
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void CallSVC(u32 swi) override {
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@ -85,11 +94,15 @@ public:
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u64 GetTicksRemaining() override {
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return ticks_remaining;
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}
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u64 GetCNTPCT() override {
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return CoreTiming::GetTicks();
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}
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ARM_Dynarmic& parent;
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size_t ticks_remaining = 0;
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size_t num_interpreted_instructions = 0;
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u64 tpidrro_el0 = 0;
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u64 tpidr_el0 = 0;
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};
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std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_Callbacks>& cb) {
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@ -98,10 +111,13 @@ std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_C
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Dynarmic::A64::UserConfig config;
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config.callbacks = cb.get();
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config.tpidrro_el0 = &cb->tpidrro_el0;
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config.tpidr_el0 = &cb->tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.page_table = reinterpret_cast<void**>(page_table);
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config.page_table_address_space_bits = Memory::ADDRESS_SPACE_BITS;
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config.silently_mirror_page_table = false;
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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