Merge pull request #288 from Subv/macro_interpreter
GPU: Implemented a gpu macro interpreter
This commit is contained in:
commit
3413f1f7ce
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@ -11,6 +11,8 @@ add_library(video_core STATIC
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engines/maxwell_compute.h
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gpu.cpp
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gpu.h
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macro_interpreter.cpp
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macro_interpreter.h
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memory_manager.cpp
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memory_manager.h
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rasterizer_interface.h
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@ -19,35 +19,21 @@ namespace Engines {
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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{0xE1A, {"BindTextureInfoBuffer", 1, &Maxwell3D::BindTextureInfoBuffer}},
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{0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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{0xE2A, {"BindStorageBuffer", 1, &Maxwell3D::BindStorageBuffer}},
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager)
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: memory_manager(memory_manager), macro_interpreter(*this) {}
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void Maxwell3D::SubmitMacroCode(u32 entry, std::vector<u32> code) {
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uploaded_macros[entry * 2 + MacroRegistersStart] = std::move(code);
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}
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void Maxwell3D::CallMacroMethod(u32 method, const std::vector<u32>& parameters) {
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// TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
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void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
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auto macro_code = uploaded_macros.find(method);
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// The requested macro must have been uploaded already.
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ASSERT_MSG(uploaded_macros.find(method) != uploaded_macros.end(), "Macro %08X was not uploaded",
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method);
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ASSERT_MSG(macro_code != uploaded_macros.end(), "Macro %08X was not uploaded", method);
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auto itr = method_handlers.find(method);
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ASSERT_MSG(itr != method_handlers.end(), "Unhandled method call %08X", method);
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ASSERT(itr->second.arguments == parameters.size());
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(this->*itr->second.handler)(parameters);
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// Reset the current macro and its parameters.
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// Reset the current macro and execute it.
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executing_macro = 0;
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macro_params.clear();
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macro_interpreter.Execute(macro_code->second, std::move(parameters));
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}
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void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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@ -77,7 +63,7 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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// Call the macro when there are no more parameters in the command buffer
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if (remaining_params == 0) {
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CallMacroMethod(executing_macro, macro_params);
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CallMacroMethod(executing_macro, std::move(macro_params));
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}
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return;
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}
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@ -193,84 +179,6 @@ void Maxwell3D::DrawArrays() {
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(false /*is_indexed*/);
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}
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void Maxwell3D::BindTextureInfoBuffer(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader stage, usually 4 for FragmentShader
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*/
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u32 stage = parameters[0];
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// Perform the same operations as the real macro code.
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GPUVAddr address = static_cast<GPUVAddr>(regs.tex_info_buffers.address[stage]) << 8;
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u32 size = regs.tex_info_buffers.size[stage];
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regs.const_buffer.cb_size = size;
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regs.const_buffer.cb_address_high = address >> 32;
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regs.const_buffer.cb_address_low = address & 0xFFFFFFFF;
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}
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void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader Program.
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* [1] = Unknown, presumably the shader id.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [3] = Shader Stage.
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* [4] = Const Buffer Address >> 8.
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*/
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auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]);
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// TODO(Subv): This address is probably an offset from the CODE_ADDRESS register.
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GPUVAddr address = parameters[2];
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auto shader_stage = static_cast<Regs::ShaderStage>(parameters[3]);
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GPUVAddr cb_address = parameters[4] << 8;
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auto& shader = state.shader_programs[static_cast<size_t>(shader_program)];
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shader.program = shader_program;
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shader.stage = shader_stage;
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shader.address = address;
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// Perform the same operations as the real macro code.
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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auto& shader_regs = regs.shader_config[static_cast<size_t>(shader_program)];
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shader_regs.start_id = address;
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// TODO(Subv): Write params[1] to register 0xD1C + shader_program.
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// TODO(Subv): Write params[2] to register 0xD22 + shader_program.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x10000;
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regs.const_buffer.cb_size = DefaultCBSize;
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regs.const_buffer.cb_address_high = cb_address >> 32;
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regs.const_buffer.cb_address_low = cb_address & 0xFFFFFFFF;
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// Write a hardcoded 0x11 to CB_BIND, this binds the current const buffer to buffer c1[] in the
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// shader. It's likely that these are the constants for the shader.
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regs.cb_bind[static_cast<size_t>(shader_stage)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_stage)].index.Assign(1);
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ProcessCBBind(shader_stage);
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}
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void Maxwell3D::BindStorageBuffer(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Buffer offset >> 2
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*/
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u32 buffer_offset = parameters[0] << 2;
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// Perform the same operations as the real macro code.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x5F00;
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regs.const_buffer.cb_size = DefaultCBSize;
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GPUVAddr address = regs.ssbo_info.BufferAddress();
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regs.const_buffer.cb_address_high = address >> 32;
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regs.const_buffer.cb_address_low = address & 0xFFFFFFFF;
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regs.const_buffer.cb_pos = buffer_offset;
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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@ -386,5 +294,10 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
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return textures;
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}
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u32 Maxwell3D::GetRegisterValue(u32 method) const {
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ASSERT_MSG(method < Regs::NUM_REGS, "Invalid Maxwell3D register");
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return regs.reg_array[method];
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}
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} // namespace Engines
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} // namespace Tegra
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@ -13,6 +13,7 @@
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#include "common/common_types.h"
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#include "common/math_util.h"
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#include "video_core/gpu.h"
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#include "video_core/macro_interpreter.h"
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#include "video_core/memory_manager.h"
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#include "video_core/textures/texture.h"
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@ -498,22 +499,18 @@ public:
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bool enabled;
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};
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struct ShaderProgramInfo {
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Regs::ShaderStage stage;
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Regs::ShaderProgram program;
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GPUVAddr address;
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};
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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std::array<ShaderStageInfo, Regs::MaxShaderStage> shader_stages;
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std::array<ShaderProgramInfo, Regs::MaxShaderProgram> shader_programs;
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};
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State state{};
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/// Reads a register value located at the input method address
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u32 GetRegisterValue(u32 method) const;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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@ -533,6 +530,9 @@ private:
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/// Parameters that have been submitted to the macro call so far.
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std::vector<u32> macro_params;
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/// Interpreter for the macro codes uploaded to the GPU.
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MacroInterpreter macro_interpreter;
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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@ -544,7 +544,7 @@ private:
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMacroMethod(u32 method, const std::vector<u32>& parameters);
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void CallMacroMethod(u32 method, std::vector<u32> parameters);
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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@ -557,19 +557,6 @@ private:
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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/// Method call handlers
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void BindTextureInfoBuffer(const std::vector<u32>& parameters);
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void SetShader(const std::vector<u32>& parameters);
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void BindStorageBuffer(const std::vector<u32>& parameters);
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struct MethodInfo {
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const char* name;
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u32 arguments;
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void (Maxwell3D::*handler)(const std::vector<u32>& parameters);
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};
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static const std::unordered_map<u32, MethodInfo> method_handlers;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -0,0 +1,257 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/macro_interpreter.h"
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namespace Tegra {
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MacroInterpreter::MacroInterpreter(Engines::Maxwell3D& maxwell3d) : maxwell3d(maxwell3d) {}
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void MacroInterpreter::Execute(const std::vector<u32>& code, std::vector<u32> parameters) {
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Reset();
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registers[1] = parameters[0];
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this->parameters = std::move(parameters);
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// Execute the code until we hit an exit condition.
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bool keep_executing = true;
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while (keep_executing) {
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keep_executing = Step(code, false);
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}
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// Assert the the macro used all the input parameters
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ASSERT(next_parameter_index == this->parameters.size());
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}
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void MacroInterpreter::Reset() {
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registers = {};
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pc = 0;
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delayed_pc = boost::none;
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method_address.raw = 0;
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parameters.clear();
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// The next parameter index starts at 1, because $r1 already has the value of the first
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// parameter.
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next_parameter_index = 1;
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}
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bool MacroInterpreter::Step(const std::vector<u32>& code, bool is_delay_slot) {
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u32 base_address = pc;
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Opcode opcode = GetOpcode(code);
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pc += 4;
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// Update the program counter if we were delayed
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if (delayed_pc != boost::none) {
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ASSERT(is_delay_slot);
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pc = *delayed_pc;
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delayed_pc = boost::none;
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}
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switch (opcode.operation) {
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case Operation::ALU: {
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u32 result = GetALUResult(opcode.alu_operation, GetRegister(opcode.src_a),
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GetRegister(opcode.src_b));
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::AddImmediate: {
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ProcessResult(opcode.result_operation, opcode.dst,
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GetRegister(opcode.src_a) + opcode.immediate);
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break;
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}
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case Operation::ExtractInsert: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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src = (src >> opcode.bf_src_bit) & opcode.GetBitfieldMask();
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dst &= ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
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dst |= src << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, dst);
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break;
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}
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case Operation::ExtractShiftLeftImmediate: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> dst) & opcode.GetBitfieldMask()) << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::ExtractShiftLeftRegister: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> opcode.bf_src_bit) & opcode.GetBitfieldMask()) << dst;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::Read: {
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u32 result = Read(GetRegister(opcode.src_a) + opcode.immediate);
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::Branch: {
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ASSERT_MSG(!is_delay_slot, "Executing a branch in a delay slot is not valid");
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u32 value = GetRegister(opcode.src_a);
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bool taken = EvaluateBranchCondition(opcode.branch_condition, value);
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if (taken) {
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// Ignore the delay slot if the branch has the annul bit.
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if (opcode.branch_annul) {
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pc = base_address + (opcode.immediate << 2);
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return true;
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}
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delayed_pc = base_address + (opcode.immediate << 2);
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// Execute one more instruction due to the delay slot.
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return Step(code, true);
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unimplemented macro operation %u",
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static_cast<u32>(opcode.operation.Value()));
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}
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if (opcode.is_exit) {
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// Exit has a delay slot, execute the next instruction
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// Note: Executing an exit during a branch delay slot will cause the instruction at the
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// branch target to be executed before exiting.
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Step(code, true);
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return false;
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}
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return true;
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}
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MacroInterpreter::Opcode MacroInterpreter::GetOpcode(const std::vector<u32>& code) const {
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ASSERT((pc % sizeof(u32)) == 0);
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ASSERT(pc < code.size() * sizeof(u32));
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return {code[pc / sizeof(u32)]};
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}
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u32 MacroInterpreter::GetALUResult(ALUOperation operation, u32 src_a, u32 src_b) const {
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switch (operation) {
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case ALUOperation::Add:
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return src_a + src_b;
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// TODO(Subv): Implement AddWithCarry
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case ALUOperation::Subtract:
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return src_a - src_b;
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// TODO(Subv): Implement SubtractWithBorrow
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case ALUOperation::Xor:
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return src_a ^ src_b;
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case ALUOperation::Or:
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return src_a | src_b;
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case ALUOperation::And:
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return src_a & src_b;
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case ALUOperation::AndNot:
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return src_a & ~src_b;
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case ALUOperation::Nand:
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return ~(src_a & src_b);
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default:
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UNIMPLEMENTED_MSG("Unimplemented ALU operation %u", static_cast<u32>(operation));
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}
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}
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void MacroInterpreter::ProcessResult(ResultOperation operation, u32 reg, u32 result) {
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switch (operation) {
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case ResultOperation::IgnoreAndFetch:
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// Fetch parameter and ignore result.
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SetRegister(reg, FetchParameter());
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break;
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case ResultOperation::Move:
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// Move result.
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SetRegister(reg, result);
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break;
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case ResultOperation::MoveAndSetMethod:
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// Move result and use as Method Address.
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SetRegister(reg, result);
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SetMethodAddress(result);
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break;
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case ResultOperation::FetchAndSend:
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// Fetch parameter and send result.
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SetRegister(reg, FetchParameter());
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Send(result);
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break;
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case ResultOperation::MoveAndSend:
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// Move and send result.
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SetRegister(reg, result);
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Send(result);
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break;
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case ResultOperation::FetchAndSetMethod:
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// Fetch parameter and use result as Method Address.
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SetRegister(reg, FetchParameter());
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SetMethodAddress(result);
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break;
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case ResultOperation::MoveAndSetMethodFetchAndSend:
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// Move result and use as Method Address, then fetch and send parameter.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send(FetchParameter());
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break;
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case ResultOperation::MoveAndSetMethodSend:
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// Move result and use as Method Address, then send bits 12:17 of result.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send((result >> 12) & 0b111111);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented result operation %u", static_cast<u32>(operation));
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}
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}
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u32 MacroInterpreter::FetchParameter() {
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ASSERT(next_parameter_index < parameters.size());
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return parameters[next_parameter_index++];
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}
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u32 MacroInterpreter::GetRegister(u32 register_id) const {
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// Register 0 is supposed to always return 0.
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if (register_id == 0)
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return 0;
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ASSERT(register_id < registers.size());
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return registers[register_id];
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}
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|
||||
void MacroInterpreter::SetRegister(u32 register_id, u32 value) {
|
||||
// Register 0 is supposed to always return 0. NOP is implemented as a store to the zero
|
||||
// register.
|
||||
if (register_id == 0)
|
||||
return;
|
||||
|
||||
ASSERT(register_id < registers.size());
|
||||
registers[register_id] = value;
|
||||
}
|
||||
|
||||
void MacroInterpreter::SetMethodAddress(u32 address) {
|
||||
method_address.raw = address;
|
||||
}
|
||||
|
||||
void MacroInterpreter::Send(u32 value) {
|
||||
maxwell3d.WriteReg(method_address.address, value, 0);
|
||||
// Increment the method address by the method increment.
|
||||
method_address.address.Assign(method_address.address.Value() +
|
||||
method_address.increment.Value());
|
||||
}
|
||||
|
||||
u32 MacroInterpreter::Read(u32 method) const {
|
||||
return maxwell3d.GetRegisterValue(method);
|
||||
}
|
||||
|
||||
bool MacroInterpreter::EvaluateBranchCondition(BranchCondition cond, u32 value) const {
|
||||
switch (cond) {
|
||||
case BranchCondition::Zero:
|
||||
return value == 0;
|
||||
case BranchCondition::NotZero:
|
||||
return value != 0;
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
|
@ -0,0 +1,164 @@
|
|||
// Copyright 2018 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <vector>
|
||||
#include <boost/optional.hpp>
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class MacroInterpreter final {
|
||||
public:
|
||||
explicit MacroInterpreter(Engines::Maxwell3D& maxwell3d);
|
||||
|
||||
/**
|
||||
* Executes the macro code with the specified input parameters.
|
||||
* @param code The macro byte code to execute
|
||||
* @param parameters The parameters of the macro
|
||||
*/
|
||||
void Execute(const std::vector<u32>& code, std::vector<u32> parameters);
|
||||
|
||||
private:
|
||||
enum class Operation : u32 {
|
||||
ALU = 0,
|
||||
AddImmediate = 1,
|
||||
ExtractInsert = 2,
|
||||
ExtractShiftLeftImmediate = 3,
|
||||
ExtractShiftLeftRegister = 4,
|
||||
Read = 5,
|
||||
Unused = 6, // This operation doesn't seem to be a valid encoding.
|
||||
Branch = 7,
|
||||
};
|
||||
|
||||
enum class ALUOperation : u32 {
|
||||
Add = 0,
|
||||
AddWithCarry = 1,
|
||||
Subtract = 2,
|
||||
SubtractWithBorrow = 3,
|
||||
// Operations 4-7 don't seem to be valid encodings.
|
||||
Xor = 8,
|
||||
Or = 9,
|
||||
And = 10,
|
||||
AndNot = 11,
|
||||
Nand = 12
|
||||
};
|
||||
|
||||
enum class ResultOperation : u32 {
|
||||
IgnoreAndFetch = 0,
|
||||
Move = 1,
|
||||
MoveAndSetMethod = 2,
|
||||
FetchAndSend = 3,
|
||||
MoveAndSend = 4,
|
||||
FetchAndSetMethod = 5,
|
||||
MoveAndSetMethodFetchAndSend = 6,
|
||||
MoveAndSetMethodSend = 7
|
||||
};
|
||||
|
||||
enum class BranchCondition : u32 {
|
||||
Zero = 0,
|
||||
NotZero = 1,
|
||||
};
|
||||
|
||||
union Opcode {
|
||||
u32 raw;
|
||||
BitField<0, 3, Operation> operation;
|
||||
BitField<4, 3, ResultOperation> result_operation;
|
||||
BitField<4, 1, BranchCondition> branch_condition;
|
||||
BitField<5, 1, u32>
|
||||
branch_annul; // If set on a branch, then the branch doesn't have a delay slot.
|
||||
BitField<7, 1, u32> is_exit;
|
||||
BitField<8, 3, u32> dst;
|
||||
BitField<11, 3, u32> src_a;
|
||||
BitField<14, 3, u32> src_b;
|
||||
// The signed immediate overlaps the second source operand and the alu operation.
|
||||
BitField<14, 18, s32> immediate;
|
||||
|
||||
BitField<17, 5, ALUOperation> alu_operation;
|
||||
|
||||
// Bitfield instructions data
|
||||
BitField<17, 5, u32> bf_src_bit;
|
||||
BitField<22, 5, u32> bf_size;
|
||||
BitField<27, 5, u32> bf_dst_bit;
|
||||
|
||||
u32 GetBitfieldMask() const {
|
||||
return (1 << bf_size) - 1;
|
||||
}
|
||||
};
|
||||
|
||||
union MethodAddress {
|
||||
u32 raw;
|
||||
BitField<0, 12, u32> address;
|
||||
BitField<12, 6, u32> increment;
|
||||
};
|
||||
|
||||
/// Resets the execution engine state, zeroing registers, etc.
|
||||
void Reset();
|
||||
|
||||
/**
|
||||
* Executes a single macro instruction located at the current program counter. Returns whether
|
||||
* the interpreter should keep running.
|
||||
* @param code The macro code to execute.
|
||||
* @param is_delay_slot Whether the current step is being executed due to a delay slot in a
|
||||
* previous instruction.
|
||||
*/
|
||||
bool Step(const std::vector<u32>& code, bool is_delay_slot);
|
||||
|
||||
/// Calculates the result of an ALU operation. src_a OP src_b;
|
||||
u32 GetALUResult(ALUOperation operation, u32 src_a, u32 src_b) const;
|
||||
|
||||
/// Performs the result operation on the input result and stores it in the specified register
|
||||
/// (if necessary).
|
||||
void ProcessResult(ResultOperation operation, u32 reg, u32 result);
|
||||
|
||||
/// Evaluates the branch condition and returns whether the branch should be taken or not.
|
||||
bool EvaluateBranchCondition(BranchCondition cond, u32 value) const;
|
||||
|
||||
/// Reads an opcode at the current program counter location.
|
||||
Opcode GetOpcode(const std::vector<u32>& code) const;
|
||||
|
||||
/// Returns the specified register's value. Register 0 is hardcoded to always return 0.
|
||||
u32 GetRegister(u32 register_id) const;
|
||||
|
||||
/// Sets the register to the input value.
|
||||
void SetRegister(u32 register_id, u32 value);
|
||||
|
||||
/// Sets the method address to use for the next Send instruction.
|
||||
void SetMethodAddress(u32 address);
|
||||
|
||||
/// Calls a GPU Engine method with the input parameter.
|
||||
void Send(u32 value);
|
||||
|
||||
/// Reads a GPU register located at the method address.
|
||||
u32 Read(u32 method) const;
|
||||
|
||||
/// Returns the next parameter in the parameter queue.
|
||||
u32 FetchParameter();
|
||||
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
|
||||
u32 pc; ///< Current program counter
|
||||
boost::optional<u32>
|
||||
delayed_pc; ///< Program counter to execute at after the delay slot is executed.
|
||||
|
||||
static constexpr size_t NumMacroRegisters = 8;
|
||||
|
||||
/// General purpose macro registers.
|
||||
std::array<u32, NumMacroRegisters> registers = {};
|
||||
|
||||
/// Method address to use for the next Send instruction.
|
||||
MethodAddress method_address = {};
|
||||
|
||||
/// Input parameters of the current macro.
|
||||
std::vector<u32> parameters;
|
||||
/// Index of the next parameter that will be fetched by the 'parm' instruction.
|
||||
u32 next_parameter_index = 0;
|
||||
};
|
||||
} // namespace Tegra
|
Reference in New Issue