shader: Implement CSET and CSETP
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32b6c63485
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@ -63,6 +63,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/common_encoding.h
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frontend/maxwell/translate/impl/common_funcs.cpp
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/condition_code_set.cpp
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frontend/maxwell/translate/impl/find_leading_one.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_compare.cpp
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@ -5,12 +5,13 @@
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#pragma once
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#include <string>
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#include <fmt/format.h>
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#include "common/common_types.h"
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namespace Shader::IR {
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enum class FlowTest {
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enum class FlowTest : u64 {
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F,
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LT,
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EQ,
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@ -169,16 +169,62 @@ void IREmitter::SetOFlag(const U1& value) {
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static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
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switch (flow_test) {
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case FlowTest::T:
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return ir.Imm1(true);
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case FlowTest::F:
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return ir.Imm1(false);
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case FlowTest::LT:
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return ir.LogicalXor(ir.LogicalAnd(ir.GetSFlag(), ir.LogicalNot(ir.GetZFlag())),
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ir.GetOFlag());
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case FlowTest::EQ:
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// TODO: Test this
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return ir.GetZFlag();
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return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.GetZFlag());
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case FlowTest::LE:
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return ir.LogicalXor(ir.GetSFlag(), ir.LogicalOr(ir.GetZFlag(), ir.GetOFlag()));
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case FlowTest::GT:
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return ir.LogicalAnd(ir.LogicalXor(ir.LogicalNot(ir.GetSFlag()), ir.GetOFlag()),
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ir.LogicalNot(ir.GetZFlag()));
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case FlowTest::NE:
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// TODO: Test this
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return ir.LogicalNot(ir.GetZFlag());
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case FlowTest::GE:
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return ir.LogicalNot(ir.LogicalXor(ir.GetSFlag(), ir.GetOFlag()));
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case FlowTest::NUM:
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return ir.LogicalOr(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag()));
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case FlowTest::NaN:
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return ir.LogicalAnd(ir.GetSFlag(), ir.GetZFlag());
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case FlowTest::LTU:
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return ir.LogicalXor(ir.GetSFlag(), ir.GetOFlag());
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case FlowTest::EQU:
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return ir.GetZFlag();
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case FlowTest::LEU:
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return ir.LogicalOr(ir.LogicalXor(ir.GetSFlag(), ir.GetOFlag()), ir.GetZFlag());
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case FlowTest::GTU:
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return ir.LogicalXor(ir.LogicalNot(ir.GetSFlag()),
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ir.LogicalOr(ir.GetZFlag(), ir.GetOFlag()));
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case FlowTest::NEU:
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return ir.LogicalOr(ir.GetSFlag(), ir.LogicalNot(ir.GetZFlag()));
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case FlowTest::GEU:
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return ir.LogicalXor(ir.LogicalOr(ir.LogicalNot(ir.GetSFlag()), ir.GetZFlag()),
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ir.GetOFlag());
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case FlowTest::T:
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return ir.Imm1(true);
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case FlowTest::OFF:
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return ir.LogicalNot(ir.GetOFlag());
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case FlowTest::LO:
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return ir.LogicalNot(ir.GetCFlag());
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case FlowTest::SFF:
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return ir.LogicalNot(ir.GetSFlag());
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case FlowTest::LS:
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return ir.LogicalOr(ir.GetZFlag(), ir.LogicalNot(ir.GetCFlag()));
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case FlowTest::HI:
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return ir.LogicalAnd(ir.GetCFlag(), ir.LogicalNot(ir.GetZFlag()));
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case FlowTest::SFT:
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return ir.GetSFlag();
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case FlowTest::HS:
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return ir.GetCFlag();
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case FlowTest::OFT:
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return ir.GetOFlag();
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case FlowTest::RLE:
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return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag());
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case FlowTest::RGT:
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return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag()));
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default:
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throw NotImplementedException("Flow test {}", flow_test);
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}
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@ -190,6 +236,10 @@ U1 IREmitter::Condition(IR::Condition cond) {
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return LogicalAnd(GetPred(pred, is_negated), GetFlowTest(*this, flow_test));
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}
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U1 IREmitter::GetFlowTestResult(FlowTest test) {
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return GetFlowTest(*this, test);
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}
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F32 IREmitter::GetAttribute(IR::Attribute attribute) {
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return Inst<F32>(Opcode::GetAttribute, attribute);
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}
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@ -62,6 +62,7 @@ public:
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void SetOFlag(const U1& value);
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[[nodiscard]] U1 Condition(IR::Condition cond);
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[[nodiscard]] U1 GetFlowTestResult(FlowTest test);
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[[nodiscard]] F32 GetAttribute(IR::Attribute attribute);
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void SetAttribute(IR::Attribute attribute, const F32& value);
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@ -0,0 +1,54 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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void TranslatorVisitor::CSET(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 5, IR::FlowTest> cc_test;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<44, 1, u64> bf;
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BitField<45, 2, BooleanOp> bop;
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} const cset{insn};
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const IR::U32 one_mask{ir.Imm32(-1)};
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const IR::U32 fp_one{ir.Imm32(0x3f800000)};
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const IR::U32 fail_result{ir.Imm32(0)};
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const IR::U32 pass_result{cset.bf == 0 ? one_mask : fp_one};
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const IR::U1 cc_test_result{ir.GetFlowTestResult(cset.cc_test)};
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const IR::U1 bop_pred{ir.GetPred(cset.bop_pred, cset.neg_bop_pred != 0)};
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const IR::U1 pred_result{PredicateCombine(ir, cc_test_result, bop_pred, cset.bop)};
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const IR::U32 result{ir.Select(pred_result, pass_result, fail_result)};
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X(cset.dest_reg, result);
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}
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void TranslatorVisitor::CSETP(u64 insn) {
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union {
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u64 raw;
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BitField<0, 3, IR::Pred> dest_pred_b;
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BitField<3, 3, IR::Pred> dest_pred_a;
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BitField<8, 5, IR::FlowTest> cc_test;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<45, 2, BooleanOp> bop;
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} const csetp{insn};
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const BooleanOp bop{csetp.bop};
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const IR::U1 bop_pred{ir.GetPred(csetp.bop_pred, csetp.neg_bop_pred != 0)};
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const IR::U1 cc_test_result{ir.GetFlowTestResult(csetp.cc_test)};
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const IR::U1 result_a{PredicateCombine(ir, cc_test_result, bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(ir, ir.LogicalNot(cc_test_result), bop_pred, bop)};
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ir.SetPred(csetp.dest_pred_a, result_a);
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ir.SetPred(csetp.dest_pred_b, result_b);
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}
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} // namespace Shader::Maxwell
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@ -85,14 +85,6 @@ void TranslatorVisitor::CS2R(u64) {
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ThrowNotImplemented(Opcode::CS2R);
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}
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void TranslatorVisitor::CSET(u64) {
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ThrowNotImplemented(Opcode::CSET);
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}
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void TranslatorVisitor::CSETP(u64) {
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ThrowNotImplemented(Opcode::CSETP);
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}
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void TranslatorVisitor::DADD_reg(u64) {
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ThrowNotImplemented(Opcode::DADD_reg);
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}
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