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@ -80,31 +80,28 @@ static Math::Vec4<u8> DecodePixel(Regs::PixelFormat input_format, const u8* src_
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MICROPROFILE_DEFINE(GPU_DisplayTransfer, "GPU", "DisplayTransfer", MP_RGB(100, 100, 255));
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MICROPROFILE_DEFINE(GPU_CmdlistProcessing, "GPU", "Cmdlist Processing", MP_RGB(100, 255, 100));
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template <typename T>
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inline void Write(u32 addr, const T data) {
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addr -= HW::VADDR_GPU;
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u32 index = addr / 4;
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static void MemoryFill(const Regs::MemoryFillConfig& config) {
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const PAddr start_addr = config.GetStartAddress();
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const PAddr end_addr = config.GetEndAddress();
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(start_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid start address 0x%08X", start_addr);
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return;
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}
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g_regs[index] = static_cast<u32>(data);
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if (!Memory::IsValidPhysicalAddress(end_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid end address 0x%08X", end_addr);
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return;
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}
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switch (index) {
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if (end_addr <= start_addr) {
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LOG_CRITICAL(HW_GPU, "invalid memory range from 0x%08X to 0x%08X", start_addr, end_addr);
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return;
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}
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// Memory fills are triggered once the fill value is written.
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
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const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
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auto& config = g_regs.memory_fill_config[is_second_filler];
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if (config.trigger) {
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if (config.address_start) { // Some games pass invalid values here
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u8* start = Memory::GetPhysicalPointer(config.GetStartAddress());
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u8* end = Memory::GetPhysicalPointer(config.GetEndAddress());
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u8* start = Memory::GetPhysicalPointer(start_addr);
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u8* end = Memory::GetPhysicalPointer(end_addr);
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// TODO: Consider always accelerating and returning vector of
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// regions that the accelerated fill did not cover to
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@ -115,10 +112,11 @@ inline void Write(u32 addr, const T data) {
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// Then fill all completely covered surfaces, and return the
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// regions that were between surfaces or within the touching
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// ones for cpu to manually fill here.
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if (!VideoCore::g_renderer->Rasterizer()->AccelerateFill(config)) {
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if (VideoCore::g_renderer->Rasterizer()->AccelerateFill(config))
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return;
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Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(),
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config.GetEndAddress() -
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config.GetStartAddress());
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config.GetEndAddress() - config.GetStartAddress());
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if (config.fill_24bit) {
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// fill with 24-bit values
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@ -141,104 +139,60 @@ inline void Write(u32 addr, const T data) {
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for (u8* ptr = start; ptr < end; ptr += sizeof(u16))
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memcpy(ptr, &value_16bit, sizeof(u16));
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}
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}
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static void DisplayTransfer(const Regs::DisplayTransferConfig& config) {
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const PAddr src_addr = config.GetPhysicalInputAddress();
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const PAddr dst_addr = config.GetPhysicalOutputAddress();
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(src_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
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return;
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}
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
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config.GetEndAddress());
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if (!is_second_filler) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
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} else {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
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}
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if (!Memory::IsValidPhysicalAddress(dst_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
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return;
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}
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// Reset "trigger" flag and set the "finish" flag
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// NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
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config.trigger.Assign(0);
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config.finished.Assign(1);
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}
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break;
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if (config.input_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero input width");
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return;
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}
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case GPU_REG_INDEX(display_transfer_config.trigger): {
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MICROPROFILE_SCOPE(GPU_DisplayTransfer);
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const auto& config = g_regs.display_transfer_config;
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if (config.trigger & 1) {
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if (Pica::g_debug_context)
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Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
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nullptr);
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if (!VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config)) {
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u8* src_pointer = Memory::GetPhysicalPointer(config.GetPhysicalInputAddress());
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u8* dst_pointer = Memory::GetPhysicalPointer(config.GetPhysicalOutputAddress());
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if (config.is_texture_copy) {
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u32 input_width = config.texture_copy.input_width * 16;
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u32 input_gap = config.texture_copy.input_gap * 16;
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u32 output_width = config.texture_copy.output_width * 16;
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u32 output_gap = config.texture_copy.output_gap * 16;
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size_t contiguous_input_size =
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config.texture_copy.size / input_width * (input_width + input_gap);
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Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
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static_cast<u32>(contiguous_input_size));
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size_t contiguous_output_size =
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config.texture_copy.size / output_width * (output_width + output_gap);
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Memory::RasterizerFlushAndInvalidateRegion(
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config.GetPhysicalOutputAddress(),
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static_cast<u32>(contiguous_output_size));
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u32 remaining_size = config.texture_copy.size;
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u32 remaining_input = input_width;
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u32 remaining_output = output_width;
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while (remaining_size > 0) {
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u32 copy_size =
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std::min({remaining_input, remaining_output, remaining_size});
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std::memcpy(dst_pointer, src_pointer, copy_size);
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src_pointer += copy_size;
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dst_pointer += copy_size;
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remaining_input -= copy_size;
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remaining_output -= copy_size;
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remaining_size -= copy_size;
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if (remaining_input == 0) {
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remaining_input = input_width;
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src_pointer += input_gap;
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}
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if (remaining_output == 0) {
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remaining_output = output_width;
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dst_pointer += output_gap;
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}
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if (config.input_height == 0) {
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LOG_CRITICAL(HW_GPU, "zero input height");
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return;
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}
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LOG_TRACE(
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HW_GPU,
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"TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> 0x%08X(%u+%u), flags 0x%08X",
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config.texture_copy.size, config.GetPhysicalInputAddress(), input_width,
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input_gap, config.GetPhysicalOutputAddress(), output_width, output_gap,
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config.flags);
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
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break;
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if (config.output_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero output width");
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return;
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}
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if (config.output_height == 0) {
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LOG_CRITICAL(HW_GPU, "zero output height");
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return;
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}
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if (VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config))
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return;
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u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
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u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
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if (config.scaling > config.ScaleXY) {
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LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u",
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config.scaling.Value());
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UNIMPLEMENTED();
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break;
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return;
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}
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if (config.input_linear && config.scaling != config.NoScale) {
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LOG_CRITICAL(HW_GPU, "Scaling is only implemented on tiled input");
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UNIMPLEMENTED();
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break;
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return;
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}
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int horizontal_scale = config.scaling != config.NoScale ? 1 : 0;
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@ -247,14 +201,12 @@ inline void Write(u32 addr, const T data) {
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u32 output_width = config.output_width >> horizontal_scale;
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u32 output_height = config.output_height >> vertical_scale;
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u32 input_size = config.input_width * config.input_height *
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GPU::Regs::BytesPerPixel(config.input_format);
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u32 output_size =
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output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
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u32 input_size =
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config.input_width * config.input_height * GPU::Regs::BytesPerPixel(config.input_format);
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u32 output_size = output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
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Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size);
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Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
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output_size);
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Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), output_size);
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for (u32 y = 0; y < output_height; ++y) {
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for (u32 x = 0; x < output_width; ++x) {
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@ -265,11 +217,14 @@ inline void Write(u32 addr, const T data) {
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u32 input_x = x << horizontal_scale;
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u32 input_y = y << vertical_scale;
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u32 output_y;
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if (config.flip_vertically) {
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// Flip the y value of the output data,
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// we do this after calculating the [x,y] position of the input image
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// to account for the scaling options.
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y = output_height - y - 1;
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output_y = output_height - y - 1;
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} else {
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output_y = y;
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}
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u32 dst_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.output_format);
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@ -280,18 +235,16 @@ inline void Write(u32 addr, const T data) {
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if (config.input_linear) {
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if (!config.dont_swizzle) {
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// Interpret the input as linear and the output as tiled
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u32 coarse_y = y & ~7;
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u32 coarse_y = output_y & ~7;
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u32 stride = output_width * dst_bytes_per_pixel;
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src_offset =
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(input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) +
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src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
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coarse_y * stride;
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} else {
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// Both input and output are linear
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src_offset =
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(input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = (x + y * output_width) * dst_bytes_per_pixel;
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src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
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}
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} else {
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if (!config.dont_swizzle) {
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@ -299,22 +252,20 @@ inline void Write(u32 addr, const T data) {
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u32 coarse_y = input_y & ~7;
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u32 stride = config.input_width * src_bytes_per_pixel;
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src_offset = VideoCore::GetMortonOffset(input_x, input_y,
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src_bytes_per_pixel) +
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src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
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coarse_y * stride;
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dst_offset = (x + y * output_width) * dst_bytes_per_pixel;
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dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
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} else {
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// Both input and output are tiled
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u32 out_coarse_y = y & ~7;
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u32 out_coarse_y = output_y & ~7;
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u32 out_stride = output_width * dst_bytes_per_pixel;
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u32 in_coarse_y = input_y & ~7;
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u32 in_stride = config.input_width * src_bytes_per_pixel;
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src_offset = VideoCore::GetMortonOffset(input_x, input_y,
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src_bytes_per_pixel) +
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src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
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in_coarse_y * in_stride;
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dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) +
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dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
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out_coarse_y * out_stride;
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}
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}
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@ -326,12 +277,12 @@ inline void Write(u32 addr, const T data) {
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DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel);
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src_color = ((src_color + pixel) / 2).Cast<u8>();
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|
} else if (config.scaling == config.ScaleXY) {
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|
Math::Vec4<u8> pixel1 = DecodePixel(
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config.input_format, src_pixel + 1 * src_bytes_per_pixel);
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Math::Vec4<u8> pixel2 = DecodePixel(
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config.input_format, src_pixel + 2 * src_bytes_per_pixel);
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|
Math::Vec4<u8> pixel3 = DecodePixel(
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config.input_format, src_pixel + 3 * src_bytes_per_pixel);
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|
Math::Vec4<u8> pixel1 =
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DecodePixel(config.input_format, src_pixel + 1 * src_bytes_per_pixel);
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|
Math::Vec4<u8> pixel2 =
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DecodePixel(config.input_format, src_pixel + 2 * src_bytes_per_pixel);
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|
Math::Vec4<u8> pixel3 =
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DecodePixel(config.input_format, src_pixel + 3 * src_bytes_per_pixel);
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|
src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>();
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|
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|
}
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|
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|
@ -364,14 +315,154 @@ inline void Write(u32 addr, const T data) {
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}
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}
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}
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}
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LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> "
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static void TextureCopy(const Regs::DisplayTransferConfig& config) {
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const PAddr src_addr = config.GetPhysicalInputAddress();
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const PAddr dst_addr = config.GetPhysicalOutputAddress();
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(src_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
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return;
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}
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if (!Memory::IsValidPhysicalAddress(dst_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
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return;
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}
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if (config.texture_copy.input_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero input width");
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return;
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}
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if (config.texture_copy.output_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero output width");
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return;
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}
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if (config.texture_copy.size == 0) {
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LOG_CRITICAL(HW_GPU, "zero size");
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|
return;
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}
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if (VideoCore::g_renderer->Rasterizer()->AccelerateTextureCopy(config))
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|
return;
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|
u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
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|
u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
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|
u32 input_width = config.texture_copy.input_width * 16;
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|
u32 input_gap = config.texture_copy.input_gap * 16;
|
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|
|
u32 output_width = config.texture_copy.output_width * 16;
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|
u32 output_gap = config.texture_copy.output_gap * 16;
|
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|
|
size_t contiguous_input_size =
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|
|
config.texture_copy.size / input_width * (input_width + input_gap);
|
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|
|
Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
|
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|
|
static_cast<u32>(contiguous_input_size));
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|
|
size_t contiguous_output_size =
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|
|
config.texture_copy.size / output_width * (output_width + output_gap);
|
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|
|
Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
|
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|
|
static_cast<u32>(contiguous_output_size));
|
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|
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|
|
u32 remaining_size = config.texture_copy.size;
|
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|
|
|
u32 remaining_input = input_width;
|
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|
|
|
u32 remaining_output = output_width;
|
|
|
|
|
while (remaining_size > 0) {
|
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|
|
|
u32 copy_size = std::min({remaining_input, remaining_output, remaining_size});
|
|
|
|
|
|
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|
|
std::memcpy(dst_pointer, src_pointer, copy_size);
|
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|
|
|
src_pointer += copy_size;
|
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|
|
|
dst_pointer += copy_size;
|
|
|
|
|
|
|
|
|
|
remaining_input -= copy_size;
|
|
|
|
|
remaining_output -= copy_size;
|
|
|
|
|
remaining_size -= copy_size;
|
|
|
|
|
|
|
|
|
|
if (remaining_input == 0) {
|
|
|
|
|
remaining_input = input_width;
|
|
|
|
|
src_pointer += input_gap;
|
|
|
|
|
}
|
|
|
|
|
if (remaining_output == 0) {
|
|
|
|
|
remaining_output = output_width;
|
|
|
|
|
dst_pointer += output_gap;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
|
inline void Write(u32 addr, const T data) {
|
|
|
|
|
addr -= HW::VADDR_GPU;
|
|
|
|
|
u32 index = addr / 4;
|
|
|
|
|
|
|
|
|
|
// Writes other than u32 are untested, so I'd rather have them abort than silently fail
|
|
|
|
|
if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
|
|
|
|
|
LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
g_regs[index] = static_cast<u32>(data);
|
|
|
|
|
|
|
|
|
|
switch (index) {
|
|
|
|
|
|
|
|
|
|
// Memory fills are triggered once the fill value is written.
|
|
|
|
|
case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
|
|
|
|
|
case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
|
|
|
|
|
const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
|
|
|
|
|
auto& config = g_regs.memory_fill_config[is_second_filler];
|
|
|
|
|
|
|
|
|
|
if (config.trigger) {
|
|
|
|
|
MemoryFill(config);
|
|
|
|
|
LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
|
|
|
|
|
config.GetEndAddress());
|
|
|
|
|
|
|
|
|
|
// It seems that it won't signal interrupt if "address_start" is zero.
|
|
|
|
|
// TODO: hwtest this
|
|
|
|
|
if (config.GetStartAddress() != 0) {
|
|
|
|
|
if (!is_second_filler) {
|
|
|
|
|
GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
|
|
|
|
|
} else {
|
|
|
|
|
GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Reset "trigger" flag and set the "finish" flag
|
|
|
|
|
// NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
|
|
|
|
|
config.trigger.Assign(0);
|
|
|
|
|
config.finished.Assign(1);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case GPU_REG_INDEX(display_transfer_config.trigger): {
|
|
|
|
|
MICROPROFILE_SCOPE(GPU_DisplayTransfer);
|
|
|
|
|
|
|
|
|
|
const auto& config = g_regs.display_transfer_config;
|
|
|
|
|
if (config.trigger & 1) {
|
|
|
|
|
|
|
|
|
|
if (Pica::g_debug_context)
|
|
|
|
|
Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
|
|
|
|
|
nullptr);
|
|
|
|
|
|
|
|
|
|
if (config.is_texture_copy) {
|
|
|
|
|
TextureCopy(config);
|
|
|
|
|
LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> "
|
|
|
|
|
"0x%08X(%u+%u), flags 0x%08X",
|
|
|
|
|
config.texture_copy.size, config.GetPhysicalInputAddress(),
|
|
|
|
|
config.texture_copy.input_width * 16, config.texture_copy.input_gap * 16,
|
|
|
|
|
config.GetPhysicalOutputAddress(), config.texture_copy.output_width * 16,
|
|
|
|
|
config.texture_copy.output_gap * 16, config.flags);
|
|
|
|
|
} else {
|
|
|
|
|
DisplayTransfer(config);
|
|
|
|
|
LOG_TRACE(HW_GPU, "DisplayTransfer: 0x%08x(%ux%u)-> "
|
|
|
|
|
"0x%08x(%ux%u), dst format %x, flags 0x%08X",
|
|
|
|
|
config.output_height * output_width *
|
|
|
|
|
GPU::Regs::BytesPerPixel(config.output_format),
|
|
|
|
|
config.GetPhysicalInputAddress(), config.input_width.Value(),
|
|
|
|
|
config.input_height.Value(), config.GetPhysicalOutputAddress(),
|
|
|
|
|
output_width, output_height, config.output_format.Value(), config.flags);
|
|
|
|
|
config.output_width.Value(), config.output_height.Value(),
|
|
|
|
|
config.output_format.Value(), config.flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
g_regs.display_transfer_config.trigger = 0;
|
|
|
|
|