Fix DMA engine register offsets
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parent
df56ecc318
commit
4f69be8169
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@ -109,10 +109,11 @@ void MaxwellDMA::Launch() {
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const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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if (regs.launch_dma.remap_enable != 0 && is_const_a_dst) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in,
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regs.remap_const.remap_consta_value);
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read_buffer.resize_destructive(regs.line_length_in * sizeof(u32));
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std::span<u32> span(reinterpret_cast<u32*>(read_buffer.data()), regs.line_length_in);
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std::ranges::fill(span, regs.remap_consta_value);
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std::ranges::fill(span, regs.remap_const.remap_consta_value);
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memory_manager.WriteBlockUnsafe(regs.offset_out,
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reinterpret_cast<u8*>(read_buffer.data()),
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regs.line_length_in * sizeof(u32));
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@ -214,14 +214,15 @@ public:
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NO_WRITE = 6,
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};
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PackedGPUVAddr address;
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u32 remap_consta_value;
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u32 remap_constb_value;
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union {
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BitField<0, 12, u32> dst_components_raw;
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BitField<0, 3, Swizzle> dst_x;
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BitField<4, 3, Swizzle> dst_y;
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BitField<8, 3, Swizzle> dst_z;
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BitField<12, 3, Swizzle> dst_w;
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BitField<0, 12, u32> dst_components_raw;
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BitField<16, 2, u32> component_size_minus_one;
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BitField<20, 2, u32> num_src_components_minus_one;
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BitField<24, 2, u32> num_dst_components_minus_one;
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@ -274,55 +275,57 @@ private:
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struct Regs {
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union {
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struct {
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u32 reserved[0x40];
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INSERT_PADDING_BYTES_NOINIT(0x100);
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u32 nop;
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u32 reserved01[0xf];
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INSERT_PADDING_BYTES_NOINIT(0x3C);
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u32 pm_trigger;
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u32 reserved02[0x3f];
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INSERT_PADDING_BYTES_NOINIT(0xFC);
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Semaphore semaphore;
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u32 reserved03[0x2];
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INSERT_PADDING_BYTES_NOINIT(0x8);
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RenderEnable render_enable;
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PhysMode src_phys_mode;
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PhysMode dst_phys_mode;
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u32 reserved04[0x26];
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INSERT_PADDING_BYTES_NOINIT(0x98);
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LaunchDMA launch_dma;
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u32 reserved05[0x3f];
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INSERT_PADDING_BYTES_NOINIT(0xFC);
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PackedGPUVAddr offset_in;
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PackedGPUVAddr offset_out;
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s32 pitch_in;
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s32 pitch_out;
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u32 line_length_in;
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u32 line_count;
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u32 reserved06[0xb6];
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u32 remap_consta_value;
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u32 remap_constb_value;
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INSERT_PADDING_BYTES_NOINIT(0x2E0);
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RemapConst remap_const;
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DMA::Parameters dst_params;
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u32 reserved07[0x1];
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INSERT_PADDING_BYTES_NOINIT(0x4);
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DMA::Parameters src_params;
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u32 reserved08[0x275];
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INSERT_PADDING_BYTES_NOINIT(0x9D4);
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u32 pm_trigger_end;
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u32 reserved09[0x3ba];
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INSERT_PADDING_BYTES_NOINIT(0xEE8);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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static_assert(sizeof(Regs) == NUM_REGS * 4);
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \
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static_assert(offsetof(MaxwellDMA::Regs, field_name) == position, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(launch_dma, 0xC0);
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ASSERT_REG_POSITION(offset_in, 0x100);
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ASSERT_REG_POSITION(offset_out, 0x102);
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ASSERT_REG_POSITION(pitch_in, 0x104);
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ASSERT_REG_POSITION(pitch_out, 0x105);
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ASSERT_REG_POSITION(line_length_in, 0x106);
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ASSERT_REG_POSITION(line_count, 0x107);
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ASSERT_REG_POSITION(remap_const, 0x1C0);
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ASSERT_REG_POSITION(dst_params, 0x1C3);
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ASSERT_REG_POSITION(src_params, 0x1CA);
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ASSERT_REG_POSITION(semaphore, 0x240);
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ASSERT_REG_POSITION(render_enable, 0x254);
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ASSERT_REG_POSITION(src_phys_mode, 0x260);
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ASSERT_REG_POSITION(launch_dma, 0x300);
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ASSERT_REG_POSITION(offset_in, 0x400);
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ASSERT_REG_POSITION(offset_out, 0x408);
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ASSERT_REG_POSITION(pitch_in, 0x410);
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ASSERT_REG_POSITION(pitch_out, 0x414);
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ASSERT_REG_POSITION(line_length_in, 0x418);
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ASSERT_REG_POSITION(line_count, 0x41C);
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ASSERT_REG_POSITION(remap_const, 0x700);
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ASSERT_REG_POSITION(dst_params, 0x70C);
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ASSERT_REG_POSITION(src_params, 0x728);
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ASSERT_REG_POSITION(pm_trigger_end, 0x1114);
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#undef ASSERT_REG_POSITION
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};
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