gl_shader_manager: Cleanup and consolidate uniform handling.
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35aca0bf1f
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51f37f5061
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@ -10,8 +10,8 @@
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namespace GLShader {
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namespace Impl {
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void SetShaderUniformBlockBinding(GLuint shader, const char* name, UniformBindings binding,
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size_t expected_size) {
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void SetShaderUniformBlockBinding(GLuint shader, const char* name,
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Maxwell3D::Regs::ShaderStage binding, size_t expected_size) {
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GLuint ub_index = glGetUniformBlockIndex(shader, name);
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if (ub_index != GL_INVALID_INDEX) {
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GLint ub_size = 0;
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@ -24,7 +24,12 @@ void SetShaderUniformBlockBinding(GLuint shader, const char* name, UniformBindin
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}
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void SetShaderUniformBlockBindings(GLuint shader) {
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SetShaderUniformBlockBinding(shader, "vs_config", UniformBindings::VS, sizeof(VSUniformData));
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SetShaderUniformBlockBinding(shader, "vs_config", Maxwell3D::Regs::ShaderStage::Vertex,
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sizeof(MaxwellUniformData));
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SetShaderUniformBlockBinding(shader, "gs_config", Maxwell3D::Regs::ShaderStage::Geometry,
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sizeof(MaxwellUniformData));
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SetShaderUniformBlockBinding(shader, "fs_config", Maxwell3D::Regs::ShaderStage::Fragment,
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sizeof(MaxwellUniformData));
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}
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void SetShaderSamplerBindings(GLuint shader) {
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@ -40,7 +45,13 @@ void SetShaderSamplerBindings(GLuint shader) {
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} // namespace Impl
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void MaxwellUniformData::SetFromRegs() {
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void MaxwellUniformData::SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage) {
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const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
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for (unsigned index = 0; index < shader_stage.const_buffers.size(); ++index) {
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const auto& const_buffer = shader_stage.const_buffers[index];
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const VAddr vaddr = memory_manager->PhysicalToVirtualAddress(const_buffer.address);
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Memory::ReadBlock(vaddr, const_buffers[index].data(), sizeof(ConstBuffer));
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}
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}
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} // namespace GLShader
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@ -14,40 +14,27 @@
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namespace GLShader {
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using Tegra::Engines::Maxwell3D;
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namespace Impl {
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void SetShaderUniformBlockBindings(GLuint shader);
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void SetShaderSamplerBindings(GLuint shader);
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} // namespace Impl
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enum class UniformBindings : GLuint { Common, VS, GS, FS };
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/// Uniform structure for the Uniform Buffer Object, all vectors must be 16-byte aligned
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// NOTE: Always keep a vec4 at the end. The GL spec is not clear wether the alignment at
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// the end of a uniform block is included in UNIFORM_BLOCK_DATA_SIZE or not.
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// Not following that rule will cause problems on some AMD drivers.
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struct MaxwellUniformData {
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void SetFromRegs();
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void SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage);
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using ConstBuffer = std::array<GLvec4, 4>;
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using Regs = Tegra::Engines::Maxwell3D::Regs;
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alignas(16) std::array<ConstBuffer, Regs::MaxConstBuffers> const_buffers;
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alignas(16) std::array<ConstBuffer, Maxwell3D::Regs::MaxConstBuffers> const_buffers;
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};
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static_assert(sizeof(MaxwellUniformData) == 1024, "MaxwellUniformData structure size is incorrect");
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static_assert(sizeof(MaxwellUniformData) < 16384,
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"MaxwellUniformData structure must be less than 16kb as per the OpenGL spec");
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struct VSUniformData {
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MaxwellUniformData uniforms;
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};
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static_assert(sizeof(VSUniformData) < 16384,
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"VSUniformData structure must be less than 16kb as per the OpenGL spec");
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struct FSUniformData {
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MaxwellUniformData uniforms;
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};
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static_assert(sizeof(FSUniformData) < 16384,
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"VSUniformData structure must be less than 16kb as per the OpenGL spec");
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class OGLShaderStage {
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public:
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OGLShaderStage() = default;
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@ -113,14 +100,14 @@ public:
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current.vs = vertex_shaders.Get(config, setup);
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}
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void UseTrivialGeometryShader() {
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current.gs = 0;
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}
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void UseProgrammableFragmentShader(const MaxwellFSConfig& config, const ShaderSetup setup) {
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current.fs = fragment_shaders.Get(config, setup);
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}
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void UseTrivialGeometryShader() {
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current.gs = 0;
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}
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void ApplyTo(OpenGLState& state) {
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// Workaround for AMD bug
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glUseProgramStages(pipeline.handle,
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