scheduler: Clear exclusive state when switching contexts
This commit is contained in:
parent
f00ca69a81
commit
56cc1c11ec
|
@ -116,6 +116,8 @@ public:
|
||||||
*/
|
*/
|
||||||
virtual void LoadContext(const ThreadContext& ctx) = 0;
|
virtual void LoadContext(const ThreadContext& ctx) = 0;
|
||||||
|
|
||||||
|
virtual void ClearExclusiveState() = 0;
|
||||||
|
|
||||||
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
||||||
virtual void PrepareReschedule() = 0;
|
virtual void PrepareReschedule() = 0;
|
||||||
};
|
};
|
||||||
|
|
|
@ -226,6 +226,10 @@ void ARM_Dynarmic::ClearInstructionCache() {
|
||||||
jit->ClearCache();
|
jit->ClearCache();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void ARM_Dynarmic::ClearExclusiveState() {
|
||||||
|
jit->ClearExclusiveState();
|
||||||
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic::PageTableChanged() {
|
void ARM_Dynarmic::PageTableChanged() {
|
||||||
jit = MakeJit(cb);
|
jit = MakeJit(cb);
|
||||||
current_page_table = Memory::GetCurrentPageTable();
|
current_page_table = Memory::GetCurrentPageTable();
|
||||||
|
|
|
@ -39,6 +39,7 @@ public:
|
||||||
void LoadContext(const ThreadContext& ctx) override;
|
void LoadContext(const ThreadContext& ctx) override;
|
||||||
|
|
||||||
void PrepareReschedule() override;
|
void PrepareReschedule() override;
|
||||||
|
void ClearExclusiveState() override;
|
||||||
|
|
||||||
void ClearInstructionCache() override;
|
void ClearInstructionCache() override;
|
||||||
void PageTableChanged() override;
|
void PageTableChanged() override;
|
||||||
|
|
|
@ -263,6 +263,8 @@ void ARM_Unicorn::PrepareReschedule() {
|
||||||
CHECKED(uc_emu_stop(uc));
|
CHECKED(uc_emu_stop(uc));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void ARM_Unicorn::ClearExclusiveState() {}
|
||||||
|
|
||||||
void ARM_Unicorn::ClearInstructionCache() {}
|
void ARM_Unicorn::ClearInstructionCache() {}
|
||||||
|
|
||||||
void ARM_Unicorn::RecordBreak(GDBStub::BreakpointAddress bkpt) {
|
void ARM_Unicorn::RecordBreak(GDBStub::BreakpointAddress bkpt) {
|
||||||
|
|
|
@ -31,6 +31,7 @@ public:
|
||||||
void SaveContext(ThreadContext& ctx) override;
|
void SaveContext(ThreadContext& ctx) override;
|
||||||
void LoadContext(const ThreadContext& ctx) override;
|
void LoadContext(const ThreadContext& ctx) override;
|
||||||
void PrepareReschedule() override;
|
void PrepareReschedule() override;
|
||||||
|
void ClearExclusiveState() override;
|
||||||
void ExecuteInstructions(int num_instructions);
|
void ExecuteInstructions(int num_instructions);
|
||||||
void Run() override;
|
void Run() override;
|
||||||
void Step() override;
|
void Step() override;
|
||||||
|
|
|
@ -85,6 +85,7 @@ void Scheduler::SwitchContext(Thread* new_thread) {
|
||||||
|
|
||||||
cpu_core->LoadContext(new_thread->context);
|
cpu_core->LoadContext(new_thread->context);
|
||||||
cpu_core->SetTlsAddress(new_thread->GetTLSAddress());
|
cpu_core->SetTlsAddress(new_thread->GetTLSAddress());
|
||||||
|
cpu_core->ClearExclusiveState();
|
||||||
} else {
|
} else {
|
||||||
current_thread = nullptr;
|
current_thread = nullptr;
|
||||||
// Note: We do not reset the current process and current page table when idling because
|
// Note: We do not reset the current process and current page table when idling because
|
||||||
|
|
Reference in New Issue