Pica: Add fog state
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c900c092e3
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57855a1701
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@ -423,6 +423,20 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[0], 0xe8):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[1], 0xe9):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[2], 0xea):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[3], 0xeb):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[4], 0xec):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[5], 0xed):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[6], 0xee):
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case PICA_REG_INDEX_WORKAROUND(fog_lut_data[7], 0xef):
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{
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g_state.fog.lut[regs.fog_lut_offset % 128].raw = value;
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regs.fog_lut_offset.Assign(regs.fog_lut_offset + 1);
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break;
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}
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default:
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break;
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}
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@ -401,22 +401,47 @@ struct Regs {
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x3);
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enum class FogMode : u32 {
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None = 0,
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Fog = 5,
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Gas = 7,
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};
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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BitField<0, 3, FogMode> fog_mode;
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BitField<16, 1, u32> fog_flip;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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};
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union {
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u32 raw;
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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} fog_color;
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INSERT_PADDING_WORDS(0x4);
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BitField<0, 16, u32> fog_lut_offset;
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INSERT_PADDING_WORDS(0x1);
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u32 fog_lut_data[8];
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INSERT_PADDING_WORDS(0xf);
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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@ -1318,6 +1343,10 @@ ASSERT_REG_POSITION(tev_stage1, 0xc8);
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ASSERT_REG_POSITION(tev_stage2, 0xd0);
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ASSERT_REG_POSITION(tev_stage3, 0xd8);
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ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(fog_mode, 0xe0);
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ASSERT_REG_POSITION(fog_color, 0xe1);
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ASSERT_REG_POSITION(fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(tev_stage4, 0xf0);
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ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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@ -33,10 +33,10 @@ struct State {
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u32 raw;
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// LUT value, encoded as 12-bit fixed point, with 12 fraction bits
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BitField< 0, 12, u32> value;
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BitField< 0, 12, u32> value; // 0.0.12 fixed point
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// Used by HW for efficient interpolation, Citra does not use these
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BitField<12, 12, u32> difference;
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BitField<12, 12, s32> difference; // 1.0.11 fixed point
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float ToFloat() {
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return static_cast<float>(value) / 4095.f;
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@ -46,6 +46,18 @@ struct State {
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std::array<std::array<LutEntry, 256>, 24> luts;
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} lighting;
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struct {
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union LutEntry {
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// Used for raw access
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u32 raw;
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BitField< 0, 13, s32> difference; // 1.1.11 fixed point
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BitField<13, 11, u32> value; // 0.0.11 fixed point
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};
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std::array<LutEntry, 128> lut;
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} fog;
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/// Current Pica command list
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struct {
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const u32* head_ptr;
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