arm_dynarmic: Support direct page table access
This commit is contained in:
parent
ce8006e851
commit
6085d32cf5
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@ -1 +1 @@
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Subproject commit 62dae592c330ab74cea30c897255ee9518639c3f
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Subproject commit cd76f5730c9a3afa19f3b9c83608d9c7ab325a19
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@ -1 +1 @@
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Subproject commit 406c07100890e0463bd3b44ff6857501cd714a93
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Subproject commit d7323d6799f0845b8c3214d624efce7a3094a657
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@ -85,11 +85,19 @@ public:
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ARM_Dynarmic& parent;
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ARM_Dynarmic& parent;
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size_t ticks_remaining = 0;
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size_t ticks_remaining = 0;
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size_t num_interpreted_instructions = 0;
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size_t num_interpreted_instructions = 0;
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u64 tpidrr0_el0 = 0;
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u64 tpidrro_el0 = 0;
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};
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};
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std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_Callbacks>& cb) {
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std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_Callbacks>& cb) {
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Dynarmic::A64::UserConfig config{cb.get()};
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const auto page_table = Kernel::g_current_process->vm_manager.page_table.pointers.data();
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Dynarmic::A64::UserConfig config;
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config.callbacks = cb.get();
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config.tpidrro_el0 = &cb->tpidrro_el0;
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config.dczid_el0 = 4;
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config.page_table = reinterpret_cast<void**>(page_table);
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config.page_table_address_space_bits = Memory::ADDRESS_SPACE_BITS;
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config.silently_mirror_page_table = false;
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return std::make_unique<Dynarmic::A64::Jit>(config);
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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}
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@ -149,11 +157,11 @@ void ARM_Dynarmic::SetCPSR(u32 cpsr) {
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}
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}
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u64 ARM_Dynarmic::GetTlsAddress() const {
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u64 ARM_Dynarmic::GetTlsAddress() const {
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return cb->tpidrr0_el0;
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return cb->tpidrro_el0;
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}
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}
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void ARM_Dynarmic::SetTlsAddress(u64 address) {
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void ARM_Dynarmic::SetTlsAddress(u64 address) {
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cb->tpidrr0_el0 = address;
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cb->tpidrro_el0 = address;
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}
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}
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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@ -170,7 +178,7 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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ctx.cpsr = jit->GetPstate();
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ctx.cpsr = jit->GetPstate();
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ctx.fpu_registers = jit->GetVectors();
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ctx.fpu_registers = jit->GetVectors();
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ctx.fpscr = jit->GetFpcr();
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ctx.fpscr = jit->GetFpcr();
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ctx.tls_address = cb->tpidrr0_el0;
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ctx.tls_address = cb->tpidrro_el0;
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}
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}
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void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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@ -180,7 +188,7 @@ void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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jit->SetPstate(static_cast<u32>(ctx.cpsr));
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jit->SetPstate(static_cast<u32>(ctx.cpsr));
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jit->SetVectors(ctx.fpu_registers);
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jit->SetVectors(ctx.fpu_registers);
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jit->SetFpcr(static_cast<u32>(ctx.fpscr));
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jit->SetFpcr(static_cast<u32>(ctx.fpscr));
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cb->tpidrr0_el0 = ctx.tls_address;
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cb->tpidrro_el0 = ctx.tls_address;
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}
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}
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void ARM_Dynarmic::PrepareReschedule() {
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void ARM_Dynarmic::PrepareReschedule() {
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@ -25,10 +25,11 @@ namespace Memory {
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* Page size used by the ARM architecture. This is the smallest granularity with which memory can
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* Page size used by the ARM architecture. This is the smallest granularity with which memory can
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* be mapped.
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* be mapped.
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*/
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*/
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const int PAGE_BITS = 12;
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constexpr size_t PAGE_BITS = 12;
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const u64 PAGE_SIZE = 1 << PAGE_BITS;
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constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
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const u64 PAGE_MASK = PAGE_SIZE - 1;
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constexpr u64 PAGE_MASK = PAGE_SIZE - 1;
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const size_t PAGE_TABLE_NUM_ENTRIES = 1ULL << (36 - PAGE_BITS);
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constexpr size_t ADDRESS_SPACE_BITS = 36;
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constexpr size_t PAGE_TABLE_NUM_ENTRIES = 1ULL << (ADDRESS_SPACE_BITS - PAGE_BITS);
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enum class PageType : u8 {
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enum class PageType : u8 {
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/// Page is unmapped and should cause an access error.
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/// Page is unmapped and should cause an access error.
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