video_core/dma_pusher: Simplyfy Step() logic.
As fetching command list headers and and the list of command headers is a fixed 1:1 relation now, they can be implemented within a single call. This cleans up the Step() logic quite a bit.
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@ -33,16 +33,34 @@ void DmaPusher::DispatchCalls() {
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}
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}
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bool DmaPusher::Step() {
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bool DmaPusher::Step() {
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if (dma_get != dma_put) {
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if (!ib_enable || dma_pushbuffer.empty()) {
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// pushbuffer empty and IB empty or nonexistent - nothing to do
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return false;
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}
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const CommandList& command_list{dma_pushbuffer.front()};
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const CommandListHeader& command_list_header{command_list[dma_pushbuffer_subindex++]};
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GPUVAddr dma_get = command_list_header.addr;
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GPUVAddr dma_put = dma_get + command_list_header.size * sizeof(u32);
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bool non_main = command_list_header.is_non_main;
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if (dma_pushbuffer_subindex >= command_list.size()) {
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// We've gone through the current list, remove it from the queue
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dma_pushbuffer.pop();
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dma_pushbuffer_subindex = 0;
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}
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if (command_list_header.size == 0) {
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return true;
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}
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// Push buffer non-empty, read a word
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// Push buffer non-empty, read a word
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const auto address = gpu.MemoryManager().GpuToCpuAddress(dma_get);
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const auto address = gpu.MemoryManager().GpuToCpuAddress(dma_get);
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ASSERT_MSG(address, "Invalid GPU address");
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ASSERT_MSG(address, "Invalid GPU address");
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GPUVAddr size = dma_put - dma_get;
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command_headers.resize(command_list_header.size);
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ASSERT_MSG(size % sizeof(CommandHeader) == 0, "Invalid aligned GPU addresses");
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command_headers.resize(size / sizeof(CommandHeader));
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Memory::ReadBlock(*address, command_headers.data(), size);
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Memory::ReadBlock(*address, command_headers.data(), command_list_header.size * sizeof(u32));
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for (const CommandHeader& command_header : command_headers) {
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for (const CommandHeader& command_header : command_headers) {
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@ -93,28 +111,9 @@ bool DmaPusher::Step() {
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}
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}
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}
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}
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dma_get = dma_put;
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if (!non_main) {
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if (!non_main) {
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// TODO (degasus): This is dead code, as dma_mget is never read.
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// TODO (degasus): This is dead code, as dma_mget is never read.
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dma_mget = dma_get;
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dma_mget = dma_put;
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}
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} else if (ib_enable && !dma_pushbuffer.empty()) {
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// Current pushbuffer empty, but we have more IB entries to read
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const CommandList& command_list{dma_pushbuffer.front()};
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const CommandListHeader& command_list_header{command_list[dma_pushbuffer_subindex++]};
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dma_get = command_list_header.addr;
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dma_put = dma_get + command_list_header.size * sizeof(u32);
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non_main = command_list_header.is_non_main;
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if (dma_pushbuffer_subindex >= command_list.size()) {
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// We've gone through the current list, remove it from the queue
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dma_pushbuffer.pop();
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dma_pushbuffer_subindex = 0;
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}
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} else {
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// Otherwise, pushbuffer empty and IB empty or nonexistent - nothing to do
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return {};
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}
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}
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return true;
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return true;
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@ -91,11 +91,8 @@ private:
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DmaState dma_state{};
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DmaState dma_state{};
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bool dma_increment_once{};
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bool dma_increment_once{};
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GPUVAddr dma_put{}; ///< pushbuffer current end address
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GPUVAddr dma_get{}; ///< pushbuffer current read address
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GPUVAddr dma_mget{}; ///< main pushbuffer last read address
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GPUVAddr dma_mget{}; ///< main pushbuffer last read address
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bool ib_enable{true}; ///< IB mode enabled
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bool ib_enable{true}; ///< IB mode enabled
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bool non_main{}; ///< non-main pushbuffer active
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};
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};
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} // namespace Tegra
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} // namespace Tegra
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