Merge pull request #1019 from Subv/vertex_divisor
Rasterizer: Manually implemented instanced rendering.
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commit
727136a9c9
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@ -222,6 +222,18 @@ void Maxwell3D::DrawArrays() {
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debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(!regs.draw.instance_next || !regs.draw.instance_cont,
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"Illegal combination of instancing parameters");
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if (regs.draw.instance_next) {
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// Increment the current instance *before* drawing.
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state.current_instance += 1;
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} else if (!regs.draw.instance_cont) {
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// Reset the current instance to 0.
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state.current_instance = 0;
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}
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const bool is_indexed{regs.index_array.count && !regs.vertex_buffer.count};
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rasterizer.AccelerateDrawBatch(is_indexed);
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@ -638,6 +638,8 @@ public:
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union {
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u32 vertex_begin_gl;
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BitField<0, 16, PrimitiveTopology> topology;
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BitField<26, 1, u32> instance_next;
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BitField<27, 1, u32> instance_cont;
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};
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} draw;
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@ -830,6 +832,7 @@ public:
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};
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std::array<ShaderStageInfo, Regs::MaxShaderStage> shader_stages;
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u32 current_instance = 0; ///< Current instance to be used to simulate instanced rendering.
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};
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State state{};
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@ -124,7 +124,7 @@ std::pair<u8*, GLintptr> RasterizerOpenGL::SetupVertexArrays(u8* array_ptr,
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glBindVertexBuffer(index, stream_buffer.GetHandle(), vertex_buffer_offset,
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vertex_array.stride);
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ASSERT_MSG(vertex_array.divisor == 0, "Vertex buffer divisor unimplemented");
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ASSERT_MSG(vertex_array.divisor == 0, "Instanced vertex arrays are not supported");
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}
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// Use the vertex array as-is, assumes that the data is formatted correctly for OpenGL.
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@ -541,7 +541,7 @@ private:
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// vertex shader, and what's the value of the fourth element when inside a Tess Eval
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// shader.
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ASSERT(stage == Maxwell3D::Regs::ShaderStage::Vertex);
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return "vec4(0, 0, uintBitsToFloat(gl_InstanceID), uintBitsToFloat(gl_VertexID))";
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return "vec4(0, 0, uintBitsToFloat(instance_id.x), uintBitsToFloat(gl_VertexID))";
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default:
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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@ -38,6 +38,7 @@ out vec4 position;
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layout (std140) uniform vs_config {
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vec4 viewport_flip;
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uvec4 instance_id;
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};
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void main() {
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@ -90,6 +91,7 @@ out vec4 color;
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layout (std140) uniform fs_config {
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vec4 viewport_flip;
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uvec4 instance_id;
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};
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void main() {
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@ -37,11 +37,16 @@ void SetShaderUniformBlockBindings(GLuint shader) {
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} // namespace Impl
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void MaxwellUniformData::SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage) {
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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const auto& gpu = Core::System::GetInstance().GPU().Maxwell3D();
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const auto& regs = gpu.regs;
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const auto& state = gpu.state;
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// TODO(bunnei): Support more than one viewport
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viewport_flip[0] = regs.viewport_transform[0].scale_x < 0.0 ? -1.0f : 1.0f;
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viewport_flip[1] = regs.viewport_transform[0].scale_y < 0.0 ? -1.0f : 1.0f;
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// We only assign the instance to the first component of the vector, the rest is just padding.
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instance_id[0] = state.current_instance;
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}
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} // namespace GLShader
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@ -24,14 +24,15 @@ void SetShaderUniformBlockBindings(GLuint shader);
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} // namespace Impl
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/// Uniform structure for the Uniform Buffer Object, all vectors must be 16-byte aligned
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// NOTE: Always keep a vec4 at the end. The GL spec is not clear wether the alignment at
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// NOTE: Always keep a vec4 at the end. The GL spec is not clear whether the alignment at
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// the end of a uniform block is included in UNIFORM_BLOCK_DATA_SIZE or not.
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// Not following that rule will cause problems on some AMD drivers.
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struct MaxwellUniformData {
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void SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage);
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alignas(16) GLvec4 viewport_flip;
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alignas(16) GLuvec4 instance_id;
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};
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static_assert(sizeof(MaxwellUniformData) == 16, "MaxwellUniformData structure size is incorrect");
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static_assert(sizeof(MaxwellUniformData) == 32, "MaxwellUniformData structure size is incorrect");
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static_assert(sizeof(MaxwellUniformData) < 16384,
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"MaxwellUniformData structure must be less than 16kb as per the OpenGL spec");
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