pica: correct bit field length for some registers
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@ -211,13 +211,14 @@ struct FramebufferRegs {
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BitField<0, 2, u32> allow_depth_stencil_write; // 0 = disable, else enable
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};
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DepthFormat depth_format; // TODO: Should be a BitField!
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BitField<0, 2, DepthFormat> depth_format;
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BitField<16, 3, ColorFormat> color_format;
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INSERT_PADDING_WORDS(0x4);
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u32 depth_buffer_address;
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u32 color_buffer_address;
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BitField<0, 28, u32> depth_buffer_address;
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BitField<0, 28, u32> color_buffer_address;
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union {
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// Apparently, the framebuffer width is stored as expected,
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@ -22,10 +22,10 @@ struct PipelineRegs {
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};
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struct {
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BitField<0, 29, u32> base_address;
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BitField<1, 28, u32> base_address;
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PAddr GetPhysicalBaseAddress() const {
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return base_address * 8;
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return base_address * 16;
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}
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// Descriptor for internal vertex attributes
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@ -99,7 +99,7 @@ struct PipelineRegs {
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// This e.g. allows to load different attributes from different memory locations
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struct {
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// Source attribute data offset from the base address
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u32 data_offset;
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BitField<0, 28, u32> data_offset;
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union {
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BitField<0, 4, u32> comp0;
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@ -180,6 +180,8 @@ struct PipelineRegs {
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// kicked off.
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// 2) Games can configure these registers to provide a command list subroutine mechanism.
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// TODO: verify the bit length of these two fields
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// According to 3dbrew, the bit length of them are 21 and 29, respectively
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BitField<0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
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BitField<0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
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u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
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@ -92,13 +92,13 @@ struct RasterizerRegs {
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BitField<0, 2, ScissorMode> mode;
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union {
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BitField<0, 16, u32> x1;
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BitField<16, 16, u32> y1;
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BitField<0, 10, u32> x1;
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BitField<16, 10, u32> y1;
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};
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union {
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BitField<0, 16, u32> x2;
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BitField<16, 16, u32> y2;
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BitField<0, 10, u32> x2;
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BitField<16, 10, u32> y2;
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};
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} scissor_test;
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@ -29,6 +29,11 @@ struct TexturingRegs {
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ClampToBorder = 1,
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Repeat = 2,
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MirroredRepeat = 3,
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// Mode 4-7 produces some weird result and may be just invalid:
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// 4: Positive coord: clamp to edge; negative coord: repeat
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// 5: Positive coord: clamp to border; negative coord: repeat
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// 6: Repeat
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// 7: Repeat
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};
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enum TextureFilter : u32 {
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@ -45,22 +50,22 @@ struct TexturingRegs {
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} border_color;
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union {
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BitField<0, 16, u32> height;
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BitField<16, 16, u32> width;
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BitField<0, 11, u32> height;
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BitField<16, 11, u32> width;
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};
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union {
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BitField<1, 1, TextureFilter> mag_filter;
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BitField<2, 1, TextureFilter> min_filter;
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BitField<8, 2, WrapMode> wrap_t;
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BitField<12, 2, WrapMode> wrap_s;
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BitField<28, 2, TextureType>
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type; ///< @note Only valid for texture 0 according to 3DBrew.
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BitField<8, 3, WrapMode> wrap_t;
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BitField<12, 3, WrapMode> wrap_s;
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/// @note Only valid for texture 0 according to 3DBrew.
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BitField<28, 3, TextureType> type;
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};
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INSERT_PADDING_WORDS(0x1);
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u32 address;
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BitField<0, 28, u32> address;
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PAddr GetPhysicalAddress() const {
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return address * 8;
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