gl_shader_decompiler: Add support for TEXS instruction.
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5ba71369ac
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8b4443c966
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@ -16,10 +16,6 @@ struct Register {
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constexpr Register(u64 value) : value(value) {}
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constexpr u64 GetIndex() const {
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return value;
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}
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constexpr operator u64() const {
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return value;
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}
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@ -71,6 +67,19 @@ union Attribute {
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u64 value;
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};
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union Sampler {
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Sampler() = default;
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constexpr Sampler(u64 value) : value(value) {}
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enum class Index : u64 {
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Sampler_0 = 8,
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};
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BitField<36, 13, Index> index;
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u64 value;
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};
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union Uniform {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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@ -295,7 +304,6 @@ union Instruction {
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<36, 13, u64> imm36;
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BitField<39, 8, Register> gpr39;
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union {
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@ -316,6 +324,7 @@ union Instruction {
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Attribute attribute;
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Uniform uniform;
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Sampler sampler;
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u64 hex;
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};
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@ -17,6 +17,7 @@ using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Sampler;
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using Tegra::Shader::SubOp;
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using Tegra::Shader::Uniform;
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@ -186,13 +187,13 @@ private:
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}
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg) {
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg.GetIndex() < 4) {
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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// GPRs 0-3 are output color for the fragment shader
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return std::string{"color."} + "rgba"[reg.GetIndex()];
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return std::string{"color."} + "rgba"[reg + elem];
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}
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return *declr_register.insert("register_" + std::to_string(reg)).first;
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return *declr_register.insert("register_" + std::to_string(reg + elem)).first;
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}
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/// Generates code representing a uniform (C buffer) register.
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@ -201,6 +202,15 @@ private:
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return 'c' + std::to_string(reg.index) + '[' + std::to_string(reg.offset) + ']';
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}
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/// Generates code representing a texture sampler.
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std::string GetSampler(const Sampler& sampler) const {
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// TODO(Subv): Support more than just texture sampler 0
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ASSERT_MSG(sampler.index == Sampler::Index::Sampler_0, "unsupported");
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const unsigned index{static_cast<unsigned>(sampler.index.Value()) -
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static_cast<unsigned>(Sampler::Index::Sampler_0)};
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return "tex[" + std::to_string(index) + "]";
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}
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/**
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* Adds code that calls a subroutine.
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* @param subroutine the subroutine to call.
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@ -245,7 +255,7 @@ private:
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switch (OpCode::GetInfo(instr.opcode).type) {
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case OpCode::Type::Arithmetic: {
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ASSERT(!instr.alu.abs_d);
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ASSERT_MSG(!instr.alu.abs_d, "unimplemented");
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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@ -330,15 +340,27 @@ private:
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::LD_A: {
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ASSERT(instr.attribute.fmt20.size == 0);
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
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break;
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}
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case OpCode::Id::ST_A: {
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ASSERT(instr.attribute.fmt20.size == 0);
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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SetDest(instr.attribute.fmt20.element, GetOutputAttribute(attribute), gpr0, 4, 1);
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break;
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}
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case OpCode::Id::TEXS: {
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ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
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const std::string op_a = GetRegister(instr.gpr8);
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const std::string op_b = GetRegister(instr.gpr20);
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const std::string sampler = GetSampler(instr.sampler);
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const std::string coord = "vec2(" + op_a + ", " + op_b + ")";
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const std::string texture = "texture(" + sampler + ", " + coord + ")";
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for (unsigned elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
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SetDest(elem, GetRegister(instr.gpr0, elem), texture, 1, 4);
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}
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled memory instruction: 0x%02x (%s): 0x%08x",
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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