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shader: Implement FMNMX 

And add a const in FCMP
This commit is contained in:
ameerj 2021-03-14 01:23:56 -05:00
parent 2d422b2498
commit 8d470c2e63
8 changed files with 101 additions and 25 deletions
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1
src/shader_recompiler/CMakeLists.txt
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@ -70,6 +70,7 @@ add_library(shader_recompiler STATIC
frontend/maxwell/translate/impl/floating_point_compare.cpp
frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
frontend/maxwell/translate/impl/floating_point_min_max.cpp
frontend/maxwell/translate/impl/floating_point_multi_function.cpp
frontend/maxwell/translate/impl/floating_point_multiply.cpp
frontend/maxwell/translate/impl/floating_point_range_reduction.cpp

8
src/shader_recompiler/backend/spirv/emit_spirv.h
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@ -162,10 +162,10 @@ Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
void EmitFPMax32(EmitContext& ctx);
void EmitFPMax64(EmitContext& ctx);
void EmitFPMin32(EmitContext& ctx);
void EmitFPMin64(EmitContext& ctx);
Id EmitFPMax32(EmitContext& ctx, Id a, Id b);
Id EmitFPMax64(EmitContext& ctx, Id a, Id b);
Id EmitFPMin32(EmitContext& ctx, Id a, Id b);
Id EmitFPMin64(EmitContext& ctx, Id a, Id b);
Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);

16
src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
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@ -60,20 +60,20 @@ Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
}
void EmitFPMax32(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitFPMax32(EmitContext& ctx, Id a, Id b) {
return ctx.OpFMax(ctx.F32[1], a, b);
}
void EmitFPMax64(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitFPMax64(EmitContext& ctx, Id a, Id b) {
return ctx.OpFMax(ctx.F64[1], a, b);
}
void EmitFPMin32(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitFPMin32(EmitContext& ctx, Id a, Id b) {
return ctx.OpFMin(ctx.F32[1], a, b);
}
void EmitFPMin64(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitFPMin64(EmitContext& ctx, Id a, Id b) {
return ctx.OpFMin(ctx.F64[1], a, b);
}
Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {

28
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@ -831,6 +831,34 @@ U1 IREmitter::FPUnordered(const F32& lhs, const F32& rhs) {
return LogicalOr(FPIsNan(lhs), FPIsNan(rhs));
}
F32F64 IREmitter::FPMax(const F32F64& lhs, const F32F64& rhs, FpControl control) {
if (lhs.Type() != rhs.Type()) {
throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
}
switch (lhs.Type()) {
case Type::F32:
return Inst<F32>(Opcode::FPMax32, Flags{control}, lhs, rhs);
case Type::F64:
return Inst<F64>(Opcode::FPMax64, Flags{control}, lhs, rhs);
default:
ThrowInvalidType(lhs.Type());
}
}
F32F64 IREmitter::FPMin(const F32F64& lhs, const F32F64& rhs, FpControl control) {
if (lhs.Type() != rhs.Type()) {
throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
}
switch (lhs.Type()) {
case Type::F32:
return Inst<F32>(Opcode::FPMin32, Flags{control}, lhs, rhs);
case Type::F64:
return Inst<F64>(Opcode::FPMin64, Flags{control}, lhs, rhs);
default:
ThrowInvalidType(lhs.Type());
}
}
U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
if (a.Type() != b.Type()) {
throw InvalidArgument("Mismatching types {} and {}", a.Type(), b.Type());

2
src/shader_recompiler/frontend/ir/ir_emitter.h
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@ -155,6 +155,8 @@ public:
[[nodiscard]] U1 FPIsNan(const F32& value);
[[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
[[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
[[nodiscard]] F32F64 FPMax(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
[[nodiscard]] F32F64 FPMin(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);

2
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_compare.cpp
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@ -88,7 +88,7 @@ void FCMP(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::F32& o
const IR::F32 zero{v.ir.Imm32(0.0f)};
const IR::F32 neg_zero{v.ir.Imm32(-0.0f)};
IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
const IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
const IR::U1 cmp_result{FloatingPointCompare(v.ir, operand, zero, fcmp.compare_op, control)};
const IR::U32 src_reg{v.X(fcmp.src_reg)};
const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};

57
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_min_max.cpp Normal file
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@ -0,0 +1,57 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void FMNMX(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> src_a_reg;
BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred;
BitField<44, 1, u64> ftz;
BitField<45, 1, u64> negate_b;
BitField<46, 1, u64> abs_a;
BitField<48, 1, u64> negate_a;
BitField<49, 1, u64> abs_b;
} const fmnmx{insn};
const IR::U1 pred{v.ir.GetPred(fmnmx.pred)};
const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fmnmx.src_a_reg), fmnmx.abs_a != 0, fmnmx.negate_a != 0)};
const IR::F32 op_b = v.ir.FPAbsNeg(src_b, fmnmx.abs_b != 0, fmnmx.negate_b != 0);
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{fmnmx.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
};
IR::F32 max{v.ir.FPMax(op_a, op_b, control)};
IR::F32 min{v.ir.FPMin(op_a, op_b, control)};
if (fmnmx.neg_pred != 0) {
std::swap(min, max);
}
v.F(fmnmx.dest_reg, IR::F32{v.ir.Select(pred, min, max)});
}
} // Anonymous namespace
void TranslatorVisitor::FMNMX_reg(u64 insn) {
FMNMX(*this, insn, GetFloatReg20(insn));
}
void TranslatorVisitor::FMNMX_cbuf(u64 insn) {
FMNMX(*this, insn, GetFloatCbuf(insn));
}
void TranslatorVisitor::FMNMX_imm(u64 insn) {
FMNMX(*this, insn, GetFloatImm20(insn));
}
} // namespace Shader::Maxwell

12
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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@ -201,18 +201,6 @@ void TranslatorVisitor::FCHK_imm(u64) {
ThrowNotImplemented(Opcode::FCHK_imm);
}
void TranslatorVisitor::FMNMX_reg(u64) {
ThrowNotImplemented(Opcode::FMNMX_reg);
}
void TranslatorVisitor::FMNMX_cbuf(u64) {
ThrowNotImplemented(Opcode::FMNMX_cbuf);
}
void TranslatorVisitor::FMNMX_imm(u64) {
ThrowNotImplemented(Opcode::FMNMX_imm);
}
void TranslatorVisitor::FSET_reg(u64) {
ThrowNotImplemented(Opcode::FSET_reg);
}