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armemu: Simplify USAT16/UXTB/UXTAB

This commit is contained in:
Lioncash 2014-12-28 11:56:16 -05:00
parent 5e16216afb
commit 914ecfe04f
1 changed files with 42 additions and 65 deletions
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53
src/core/arm/interpreter/armemu.cpp
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@ -6422,29 +6422,12 @@ L_stm_s_takeabort:
return 1; return 1;
} }
break; break;
case 0x6e: { case 0x6e: // USAT, USAT16, UXTB, and UXTAB
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) {
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0x01:
case 0xf3:
//ichfly
//USAT16
{ {
const u8 op2 = BITS(5, 7);
// USAT16
if (op2 == 0x01) {
const u8 rd_idx = BITS(12, 15); const u8 rd_idx = BITS(12, 15);
const u8 rn_idx = BITS(0, 3); const u8 rn_idx = BITS(0, 3);
const u8 num_bits = BITS(16, 19); const u8 num_bits = BITS(16, 19);
@ -6471,30 +6454,24 @@ L_stm_s_takeabort:
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF); state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
return 1; return 1;
} }
else if (op2 == 0x03) {
default: const u8 rotate = BITS(10, 11) * 8;
break; const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF);
}
if (ror == -1) {
if (BITS(4, 6) == 0x7) {
printf("Unhandled v6 insn: usat\n");
return 0;
}
break;
}
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
if (BITS(16, 19) == 0xf) if (BITS(16, 19) == 0xf)
/* UXTB */ /* UXTB */
state->Reg[BITS(12, 15)] = Rm; state->Reg[BITS(12, 15)] = rm;
else else
/* UXTAB */ /* UXTAB */
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm; state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
return 1; return 1;
} }
else {
printf("Unimplemented op: USAT");
}
}
break;
case 0x6f: // UXTH, UXTAH, and REVSH. case 0x6f: // UXTH, UXTAH, and REVSH.
{ {