Merge pull request #11902 from ameerj/ssbo-align
shader_recompiler: Align SSBO offsets to meet host requirements
This commit is contained in:
commit
992ca8c358
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@ -5,6 +5,7 @@
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#include "shader_recompiler/backend/glasm/glasm_emit_context.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/profile.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Backend::GLASM {
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@ -35,7 +36,9 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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continue;
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}
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const auto& ssbo{ctx.info.storage_buffers_descriptors[index]};
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // ssbo_addr
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const u64 ssbo_align_mask{~(ctx.profile.min_ssbo_alignment - 1U)};
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // unaligned_ssbo_addr
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"AND.U64 DC.x,DC.x,{};" // ssbo_addr = unaligned_ssbo_addr & ssbo_align_mask
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"LDC.U32 RC.x,c{}[{}];" // ssbo_size_u32
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"CVT.U64.U32 DC.y,RC.x;" // ssbo_size = ssbo_size_u32
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"ADD.U64 DC.y,DC.y,DC.x;" // ssbo_end = ssbo_addr + ssbo_size
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@ -44,8 +47,8 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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"AND.U.CC RC.x,RC.x,RC.y;" // cond = a && b
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"IF NE.x;" // if cond
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"SUB.U64 DC.x,{}.x,DC.x;", // offset = input_addr - ssbo_addr
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo.cbuf_index, ssbo.cbuf_offset + 8, address,
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address, address);
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo_align_mask, ssbo.cbuf_index,
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ssbo.cbuf_offset + 8, address, address, address);
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if (pointer_based) {
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ctx.Add("PK64.U DC.y,c[{}];" // host_ssbo = cbuf
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"ADD.U64 DC.x,DC.x,DC.y;" // host_addr = host_ssbo + offset
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@ -601,7 +601,10 @@ std::string EmitContext::DefineGlobalMemoryFunctions() {
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addr_xy[i] = fmt::format("ftou({}[{}].{})", cbuf, addr_loc / 16, Swizzle(addr_loc));
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size_xy[i] = fmt::format("ftou({}[{}].{})", cbuf, size_loc / 16, Swizzle(size_loc));
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}
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const auto addr_pack{fmt::format("packUint2x32(uvec2({},{}))", addr_xy[0], addr_xy[1])};
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const u32 ssbo_align_mask{~(static_cast<u32>(profile.min_ssbo_alignment) - 1U)};
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const auto aligned_low_addr{fmt::format("{}&{}", addr_xy[0], ssbo_align_mask)};
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const auto aligned_addr{fmt::format("uvec2({},{})", aligned_low_addr, addr_xy[1])};
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const auto addr_pack{fmt::format("packUint2x32({})", aligned_addr)};
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const auto addr_statment{fmt::format("uint64_t {}={};", ssbo_addr, addr_pack)};
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func += addr_statment;
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@ -891,7 +891,9 @@ void EmitContext::DefineGlobalMemoryFunctions(const Info& info) {
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const Id ssbo_size_pointer{OpAccessChain(uniform_types.U32, cbufs[ssbo.cbuf_index].U32,
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zero, ssbo_size_cbuf_offset)};
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const Id ssbo_addr{OpBitcast(U64, OpLoad(U32[2], ssbo_addr_pointer))};
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const u64 ssbo_align_mask{~(profile.min_ssbo_alignment - 1U)};
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const Id unaligned_addr{OpBitcast(U64, OpLoad(U32[2], ssbo_addr_pointer))};
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const Id ssbo_addr{OpBitwiseAnd(U64, unaligned_addr, Constant(U64, ssbo_align_mask))};
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const Id ssbo_size{OpUConvert(U64, OpLoad(U32[1], ssbo_size_pointer))};
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const Id ssbo_end{OpIAdd(U64, ssbo_addr, ssbo_size)};
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const Id cond{OpLogicalAnd(U1, OpUGreaterThanEqual(U1, addr, ssbo_addr),
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@ -298,7 +298,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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Optimization::PositionPass(env, program);
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Optimization::GlobalMemoryToStorageBufferPass(program);
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Optimization::GlobalMemoryToStorageBufferPass(program, host_info);
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Optimization::TexturePass(env, program, host_info);
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if (Settings::values.resolution_info.active) {
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@ -16,6 +16,7 @@ struct HostTranslateInfo {
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bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
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bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
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bool support_viewport_index_layer{}; ///< True when the device supports gl_Layer in VS
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u32 min_ssbo_alignment{}; ///< Minimum alignment supported by the device for SSBOs
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bool support_geometry_shader_passthrough{}; ///< True when the device supports geometry
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///< passthrough shaders
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bool support_conditional_barrier{}; ///< True when the device supports barriers in conditional
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@ -11,6 +11,7 @@
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#include "shader_recompiler/frontend/ir/breadth_first_search.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Optimization {
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@ -408,7 +409,7 @@ void CollectStorageBuffers(IR::Block& block, IR::Inst& inst, StorageInfo& info)
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}
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/// Returns the offset in indices (not bytes) for an equivalent storage instruction
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IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer) {
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IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer, u32 alignment) {
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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IR::U32 offset;
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if (const std::optional<LowAddrInfo> low_addr{TrackLowAddress(&inst)}) {
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@ -421,7 +422,10 @@ IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer
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}
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// Subtract the least significant 32 bits from the guest offset. The result is the storage
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// buffer offset in bytes.
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const IR::U32 low_cbuf{ir.GetCbuf(ir.Imm32(buffer.index), ir.Imm32(buffer.offset))};
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IR::U32 low_cbuf{ir.GetCbuf(ir.Imm32(buffer.index), ir.Imm32(buffer.offset))};
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// Align the offset base to match the host alignment requirements
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low_cbuf = ir.BitwiseAnd(low_cbuf, ir.Imm32(~(alignment - 1U)));
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return ir.ISub(offset, low_cbuf);
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}
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@ -516,7 +520,7 @@ void Replace(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
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}
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} // Anonymous namespace
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void GlobalMemoryToStorageBufferPass(IR::Program& program) {
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void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info) {
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StorageInfo info;
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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@ -540,7 +544,8 @@ void GlobalMemoryToStorageBufferPass(IR::Program& program) {
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const IR::U32 index{IR::Value{static_cast<u32>(info.set.index_of(it))}};
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IR::Block* const block{storage_inst.block};
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IR::Inst* const inst{storage_inst.inst};
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const IR::U32 offset{StorageOffset(*block, *inst, storage_buffer)};
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const IR::U32 offset{
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StorageOffset(*block, *inst, storage_buffer, host_info.min_ssbo_alignment)};
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Replace(*block, *inst, index, offset);
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}
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}
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@ -16,7 +16,7 @@ void CollectShaderInfoPass(Environment& env, IR::Program& program);
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void ConditionalBarrierPass(IR::Program& program);
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void ConstantPropagationPass(Environment& env, IR::Program& program);
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void DeadCodeEliminationPass(IR::Program& program);
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void GlobalMemoryToStorageBufferPass(IR::Program& program);
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void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info);
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void IdentityRemovalPass(IR::Program& program);
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void LowerFp64ToFp32(IR::Program& program);
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void LowerFp16ToFp32(IR::Program& program);
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@ -85,6 +85,8 @@ struct Profile {
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/// Maxwell and earlier nVidia architectures have broken robust support
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bool has_broken_robust{};
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u64 min_ssbo_alignment{};
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};
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} // namespace Shader
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@ -1753,15 +1753,25 @@ Binding BufferCache<P>::StorageBufferBinding(GPUVAddr ssbo_addr, u32 cbuf_index,
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const u32 memory_layout_size = static_cast<u32>(gpu_memory->GetMemoryLayoutSize(gpu_addr));
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return std::min(memory_layout_size, static_cast<u32>(8_MiB));
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}();
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const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr);
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if (!cpu_addr || size == 0) {
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// Alignment only applies to the offset of the buffer
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const u32 alignment = runtime.GetStorageBufferAlignment();
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const GPUVAddr aligned_gpu_addr = Common::AlignDown(gpu_addr, alignment);
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const u32 aligned_size = static_cast<u32>(gpu_addr - aligned_gpu_addr) + size;
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const std::optional<VAddr> aligned_cpu_addr = gpu_memory->GpuToCpuAddress(aligned_gpu_addr);
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if (!aligned_cpu_addr || size == 0) {
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LOG_WARNING(HW_GPU, "Failed to find storage buffer for cbuf index {}", cbuf_index);
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return NULL_BINDING;
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}
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const VAddr cpu_end = Common::AlignUp(*cpu_addr + size, YUZU_PAGESIZE);
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const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr);
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ASSERT_MSG(cpu_addr, "Unaligned storage buffer address not found for cbuf index {}",
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cbuf_index);
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// The end address used for size calculation does not need to be aligned
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const VAddr cpu_end = Common::AlignUp(*cpu_addr + size, Core::Memory::YUZU_PAGESIZE);
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const Binding binding{
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.cpu_addr = *cpu_addr,
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.size = is_written ? size : static_cast<u32>(cpu_end - *cpu_addr),
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.cpu_addr = *aligned_cpu_addr,
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.size = is_written ? aligned_size : static_cast<u32>(cpu_end - *aligned_cpu_addr),
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.buffer_id = BufferId{},
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};
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return binding;
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@ -191,6 +191,10 @@ public:
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return device.CanReportMemoryUsage();
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}
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u32 GetStorageBufferAlignment() const {
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return static_cast<u32>(device.GetShaderStorageBufferAlignment());
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}
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private:
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static constexpr std::array PABO_LUT{
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GL_VERTEX_PROGRAM_PARAMETER_BUFFER_NV, GL_TESS_CONTROL_PROGRAM_PARAMETER_BUFFER_NV,
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@ -232,6 +232,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.has_gl_bool_ref_bug = device.HasBoolRefBug(),
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.ignore_nan_fp_comparisons = true,
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.gl_max_compute_smem_size = device.GetMaxComputeSharedMemorySize(),
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.min_ssbo_alignment = device.GetShaderStorageBufferAlignment(),
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},
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host_info{
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.support_float64 = true,
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@ -240,6 +241,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.needs_demote_reorder = device.IsAmd(),
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.support_snorm_render_buffer = false,
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.support_viewport_index_layer = device.HasVertexViewportLayer(),
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.min_ssbo_alignment = static_cast<u32>(device.GetShaderStorageBufferAlignment()),
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.support_geometry_shader_passthrough = device.HasGeometryShaderPassthrough(),
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.support_conditional_barrier = device.SupportsConditionalBarriers(),
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} {
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@ -355,6 +355,10 @@ bool BufferCacheRuntime::CanReportMemoryUsage() const {
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return device.CanReportMemoryUsage();
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}
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u32 BufferCacheRuntime::GetStorageBufferAlignment() const {
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return static_cast<u32>(device.GetStorageBufferAlignment());
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}
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void BufferCacheRuntime::TickFrame(VideoCommon::SlotVector<Buffer>& slot_buffers) noexcept {
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for (auto it = slot_buffers.begin(); it != slot_buffers.end(); it++) {
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it->ResetUsageTracking();
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@ -91,6 +91,8 @@ public:
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bool CanReportMemoryUsage() const;
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u32 GetStorageBufferAlignment() const;
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[[nodiscard]] StagingBufferRef UploadStagingBuffer(size_t size);
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[[nodiscard]] StagingBufferRef DownloadStagingBuffer(size_t size, bool deferred = false);
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@ -373,6 +373,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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.has_broken_robust =
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device.IsNvidia() && device.GetNvidiaArch() <= NvidiaArchitecture::Arch_Pascal,
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.min_ssbo_alignment = device.GetStorageBufferAlignment(),
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};
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host_info = Shader::HostTranslateInfo{
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@ -383,6 +384,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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driver_id == VK_DRIVER_ID_AMD_PROPRIETARY || driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE,
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.support_snorm_render_buffer = true,
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.support_viewport_index_layer = device.IsExtShaderViewportIndexLayerSupported(),
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.min_ssbo_alignment = static_cast<u32>(device.GetStorageBufferAlignment()),
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.support_geometry_shader_passthrough = device.IsNvGeometryShaderPassthroughSupported(),
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.support_conditional_barrier = device.SupportsConditionalBarriers(),
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};
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