Merge pull request #9363 from liamwhite/gs
shader_recompiler: add gl_Layer translation GS for older hardware
This commit is contained in:
commit
9a5d8b356a
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@ -221,6 +221,7 @@ add_library(shader_recompiler STATIC
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ir_opt/dual_vertex_pass.cpp
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ir_opt/global_memory_to_storage_buffer_pass.cpp
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ir_opt/identity_removal_pass.cpp
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ir_opt/layer_pass.cpp
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ir_opt/lower_fp16_to_fp32.cpp
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ir_opt/lower_int64_to_int32.cpp
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ir_opt/passes.h
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@ -9,6 +9,7 @@
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#include "common/settings.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/post_order.h"
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#include "shader_recompiler/frontend/maxwell/structured_control_flow.h"
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#include "shader_recompiler/frontend/maxwell/translate/translate.h"
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@ -233,6 +234,8 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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Optimization::VerificationPass(program);
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}
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Optimization::CollectShaderInfoPass(env, program);
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Optimization::LayerPass(program, host_info);
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CollectInterpolationInfo(env, program);
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AddNVNStorageBuffers(program);
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return program;
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@ -331,4 +334,82 @@ void ConvertLegacyToGeneric(IR::Program& program, const Shader::RuntimeInfo& run
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}
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}
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IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology) {
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IR::Program program;
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program.stage = Stage::Geometry;
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program.output_topology = output_topology;
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switch (output_topology) {
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case OutputTopology::PointList:
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program.output_vertices = 1;
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break;
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case OutputTopology::LineStrip:
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program.output_vertices = 2;
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break;
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default:
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program.output_vertices = 3;
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break;
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}
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program.is_geometry_passthrough = false;
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program.info.loads.mask = source_program.info.stores.mask;
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program.info.stores.mask = source_program.info.stores.mask;
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program.info.stores.Set(IR::Attribute::Layer, true);
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program.info.stores.Set(source_program.info.emulated_layer, false);
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IR::Block* current_block = block_pool.Create(inst_pool);
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auto& node{program.syntax_list.emplace_back()};
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node.type = IR::AbstractSyntaxNode::Type::Block;
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node.data.block = current_block;
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IR::IREmitter ir{*current_block};
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for (u32 i = 0; i < program.output_vertices; i++) {
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// Assign generics from input
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for (u32 j = 0; j < 32; j++) {
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if (!program.info.stores.Generic(j)) {
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continue;
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}
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const IR::Attribute attr = IR::Attribute::Generic0X + (j * 4);
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ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
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}
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// Assign position from input
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const IR::Attribute attr = IR::Attribute::PositionX;
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ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
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ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
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// Assign layer
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ir.SetAttribute(IR::Attribute::Layer, ir.GetAttribute(source_program.info.emulated_layer),
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ir.Imm32(0));
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// Emit vertex
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ir.EmitVertex(ir.Imm32(0));
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}
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ir.EndPrimitive(ir.Imm32(0));
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IR::Block* return_block{block_pool.Create(inst_pool)};
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IR::IREmitter{*return_block}.Epilogue();
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current_block->AddBranch(return_block);
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auto& merge{program.syntax_list.emplace_back()};
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merge.type = IR::AbstractSyntaxNode::Type::Block;
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merge.data.block = return_block;
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program.syntax_list.emplace_back().type = IR::AbstractSyntaxNode::Type::Return;
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program.blocks = GenerateBlocks(program.syntax_list);
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program.post_order_blocks = PostOrder(program.syntax_list.front());
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Optimization::SsaRewritePass(program);
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return program;
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}
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} // namespace Shader::Maxwell
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@ -25,4 +25,13 @@ namespace Shader::Maxwell {
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void ConvertLegacyToGeneric(IR::Program& program, const RuntimeInfo& runtime_info);
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// Maxwell v1 and older Nvidia cards don't support setting gl_Layer from non-geometry stages.
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// This creates a workaround by setting the layer as a generic output and creating a
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// passthrough geometry shader that reads the generic and sets the layer.
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[[nodiscard]] IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology);
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} // namespace Shader::Maxwell
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@ -13,7 +13,8 @@ struct HostTranslateInfo {
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bool support_float16{}; ///< True when the device supports 16-bit floats
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bool support_int64{}; ///< True when the device supports 64-bit integers
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bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
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bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
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bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
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bool support_viewport_index_layer{}; ///< True when the device supports gl_Layer in VS
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};
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} // namespace Shader
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@ -0,0 +1,68 @@
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// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <algorithm>
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#include <bit>
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#include <optional>
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#include <boost/container/small_vector.hpp>
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#include "shader_recompiler/environment.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/breadth_first_search.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/ir_opt/passes.h"
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#include "shader_recompiler/shader_info.h"
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namespace Shader::Optimization {
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static IR::Attribute EmulatedLayerAttribute(VaryingState& stores) {
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for (u32 i = 0; i < 32; i++) {
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if (!stores.Generic(i)) {
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return IR::Attribute::Generic0X + (i * 4);
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}
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}
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return IR::Attribute::Layer;
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}
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static bool PermittedProgramStage(Stage stage) {
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switch (stage) {
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case Stage::VertexA:
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case Stage::VertexB:
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case Stage::TessellationControl:
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case Stage::TessellationEval:
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return true;
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default:
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return false;
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}
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}
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void LayerPass(IR::Program& program, const HostTranslateInfo& host_info) {
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if (host_info.support_viewport_index_layer || !PermittedProgramStage(program.stage)) {
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return;
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}
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const auto end{program.post_order_blocks.end()};
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const auto layer_attribute = EmulatedLayerAttribute(program.info.stores);
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bool requires_layer_emulation = false;
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for (auto block = program.post_order_blocks.begin(); block != end; ++block) {
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for (IR::Inst& inst : (*block)->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::SetAttribute &&
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inst.Arg(0).Attribute() == IR::Attribute::Layer) {
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requires_layer_emulation = true;
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inst.SetArg(0, IR::Value{layer_attribute});
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}
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}
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}
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if (requires_layer_emulation) {
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program.info.requires_layer_emulation = true;
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program.info.emulated_layer = layer_attribute;
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program.info.stores.Set(IR::Attribute::Layer, false);
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program.info.stores.Set(layer_attribute, true);
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}
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}
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} // namespace Shader::Optimization
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@ -23,6 +23,7 @@ void RescalingPass(IR::Program& program);
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void SsaRewritePass(IR::Program& program);
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void PositionPass(Environment& env, IR::Program& program);
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void TexturePass(Environment& env, IR::Program& program, const HostTranslateInfo& host_info);
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void LayerPass(IR::Program& program, const HostTranslateInfo& host_info);
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void VerificationPass(const IR::Program& program);
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// Dual Vertex
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@ -204,6 +204,9 @@ struct Info {
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u32 nvn_buffer_base{};
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std::bitset<16> nvn_buffer_used{};
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bool requires_layer_emulation{};
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IR::Attribute emulated_layer{};
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boost::container::static_vector<ConstantBufferDescriptor, MAX_CBUFS>
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constant_buffer_descriptors;
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boost::container::static_vector<StorageBufferDescriptor, MAX_SSBOS> storage_buffers_descriptors;
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@ -39,6 +39,7 @@ using Shader::Backend::GLASM::EmitGLASM;
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using Shader::Backend::GLSL::EmitGLSL;
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using Shader::Backend::SPIRV::EmitSPIRV;
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using Shader::Maxwell::ConvertLegacyToGeneric;
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using Shader::Maxwell::GenerateGeometryPassthrough;
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using Shader::Maxwell::MergeDualVertexPrograms;
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using Shader::Maxwell::TranslateProgram;
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using VideoCommon::ComputeEnvironment;
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@ -56,6 +57,17 @@ auto MakeSpan(Container& container) {
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return std::span(container.data(), container.size());
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}
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Shader::OutputTopology MaxwellToOutputTopology(Maxwell::PrimitiveTopology topology) {
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switch (topology) {
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case Maxwell::PrimitiveTopology::Points:
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return Shader::OutputTopology::PointList;
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case Maxwell::PrimitiveTopology::LineStrip:
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return Shader::OutputTopology::LineStrip;
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default:
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return Shader::OutputTopology::TriangleStrip;
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}
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}
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Shader::RuntimeInfo MakeRuntimeInfo(const GraphicsPipelineKey& key,
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const Shader::IR::Program& program,
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const Shader::IR::Program* previous_program,
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@ -220,6 +232,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.support_int64 = device.HasShaderInt64(),
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.needs_demote_reorder = device.IsAmd(),
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.support_snorm_render_buffer = false,
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.support_viewport_index_layer = device.HasVertexViewportLayer(),
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} {
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if (use_asynchronous_shaders) {
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workers = CreateWorkers();
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@ -314,9 +327,7 @@ GraphicsPipeline* ShaderCache::CurrentGraphicsPipeline() {
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const auto& regs{maxwell3d->regs};
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graphics_key.raw = 0;
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graphics_key.early_z.Assign(regs.mandated_early_z != 0 ? 1 : 0);
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graphics_key.gs_input_topology.Assign(graphics_key.unique_hashes[4] != 0
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? regs.draw.topology.Value()
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: Maxwell::PrimitiveTopology{});
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graphics_key.gs_input_topology.Assign(regs.draw.topology.Value());
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graphics_key.tessellation_primitive.Assign(regs.tessellation.params.domain_type.Value());
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graphics_key.tessellation_spacing.Assign(regs.tessellation.params.spacing.Value());
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graphics_key.tessellation_clockwise.Assign(
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@ -415,7 +426,19 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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std::array<Shader::IR::Program, Maxwell::MaxShaderProgram> programs;
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const bool uses_vertex_a{key.unique_hashes[0] != 0};
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const bool uses_vertex_b{key.unique_hashes[1] != 0};
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// Layer passthrough generation for devices without GL_ARB_shader_viewport_layer_array
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Shader::IR::Program* layer_source_program{};
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for (size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
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const bool is_emulated_stage = layer_source_program != nullptr &&
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && is_emulated_stage) {
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auto topology = MaxwellToOutputTopology(key.gs_input_topology);
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programs[index] = GenerateGeometryPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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continue;
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}
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if (key.unique_hashes[index] == 0) {
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continue;
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}
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@ -443,6 +466,10 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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Shader::NumDescriptors(program_vb.info.storage_buffers_descriptors);
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programs[index] = MergeDualVertexPrograms(program_va, program_vb, env);
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}
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if (programs[index].info.requires_layer_emulation) {
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layer_source_program = &programs[index];
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}
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}
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const u32 glasm_storage_buffer_limit{device.GetMaxGLASMStorageBufferBlocks()};
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const bool glasm_use_storage_buffers{total_storage_buffers <= glasm_storage_buffer_limit};
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@ -456,7 +483,9 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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const bool use_glasm{device.UseAssemblyShaders()};
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const size_t first_index = uses_vertex_a && uses_vertex_b ? 1 : 0;
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for (size_t index = first_index; index < Maxwell::MaxShaderProgram; ++index) {
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if (key.unique_hashes[index] == 0) {
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const bool is_emulated_stage = layer_source_program != nullptr &&
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && !is_emulated_stage) {
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continue;
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}
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UNIMPLEMENTED_IF(index == 0);
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@ -46,6 +46,7 @@ MICROPROFILE_DECLARE(Vulkan_PipelineCache);
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namespace {
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using Shader::Backend::SPIRV::EmitSPIRV;
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using Shader::Maxwell::ConvertLegacyToGeneric;
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using Shader::Maxwell::GenerateGeometryPassthrough;
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using Shader::Maxwell::MergeDualVertexPrograms;
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using Shader::Maxwell::TranslateProgram;
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using VideoCommon::ComputeEnvironment;
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@ -60,6 +61,17 @@ auto MakeSpan(Container& container) {
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return std::span(container.data(), container.size());
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}
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Shader::OutputTopology MaxwellToOutputTopology(Maxwell::PrimitiveTopology topology) {
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switch (topology) {
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case Maxwell::PrimitiveTopology::Points:
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return Shader::OutputTopology::PointList;
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case Maxwell::PrimitiveTopology::LineStrip:
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return Shader::OutputTopology::LineStrip;
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default:
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return Shader::OutputTopology::TriangleStrip;
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}
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}
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Shader::CompareFunction MaxwellToCompareFunction(Maxwell::ComparisonOp comparison) {
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switch (comparison) {
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case Maxwell::ComparisonOp::Never_D3D:
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@ -327,6 +339,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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.needs_demote_reorder = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY_KHR ||
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driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE_KHR,
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.support_snorm_render_buffer = true,
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.support_viewport_index_layer = device.IsExtShaderViewportIndexLayerSupported(),
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};
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}
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@ -509,7 +522,19 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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std::array<Shader::IR::Program, Maxwell::MaxShaderProgram> programs;
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const bool uses_vertex_a{key.unique_hashes[0] != 0};
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const bool uses_vertex_b{key.unique_hashes[1] != 0};
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// Layer passthrough generation for devices without VK_EXT_shader_viewport_index_layer
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Shader::IR::Program* layer_source_program{};
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for (size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
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const bool is_emulated_stage = layer_source_program != nullptr &&
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && is_emulated_stage) {
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auto topology = MaxwellToOutputTopology(key.state.topology);
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programs[index] = GenerateGeometryPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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continue;
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}
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if (key.unique_hashes[index] == 0) {
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continue;
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}
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@ -530,6 +555,10 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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auto program_vb{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
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programs[index] = MergeDualVertexPrograms(program_va, program_vb, env);
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}
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if (programs[index].info.requires_layer_emulation) {
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layer_source_program = &programs[index];
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}
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}
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std::array<const Shader::Info*, Maxwell::MaxShaderStage> infos{};
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std::array<vk::ShaderModule, Maxwell::MaxShaderStage> modules;
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@ -538,7 +567,9 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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Shader::Backend::Bindings binding;
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for (size_t index = uses_vertex_a && uses_vertex_b ? 1 : 0; index < Maxwell::MaxShaderProgram;
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++index) {
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if (key.unique_hashes[index] == 0) {
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const bool is_emulated_stage = layer_source_program != nullptr &&
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && !is_emulated_stage) {
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continue;
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}
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UNIMPLEMENTED_IF(index == 0);
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