shader: Read branch conditions from an instruction
Fixes the identity removal pass.
This commit is contained in:
parent
4bad415bca
commit
9bb3e008c9
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@ -200,7 +200,7 @@ void Precolor(EmitContext& ctx, const IR::Program& program) {
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}
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}
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// Add reference to the phi node on the phi predecessor to avoid overwritting it
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// Add reference to the phi node on the phi predecessor to avoid overwritting it
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for (size_t i = 0; i < num_args; ++i) {
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for (size_t i = 0; i < num_args; ++i) {
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IR::IREmitter{*phi.PhiBlock(i)}.DummyReference(IR::Value{&phi});
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IR::IREmitter{*phi.PhiBlock(i)}.Reference(IR::Value{&phi});
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}
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}
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}
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}
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}
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}
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@ -22,6 +22,10 @@ void EmitIdentity(EmitContext&, IR::Inst& inst, const IR::Value& value) {
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Alias(inst, value);
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Alias(inst, value);
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}
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}
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void EmitConditionRef(EmitContext&, IR::Inst& inst, const IR::Value& value) {
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Alias(inst, value);
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}
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void EmitBitCastU16F16(EmitContext&, IR::Inst& inst, const IR::Value& value) {
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void EmitBitCastU16F16(EmitContext&, IR::Inst& inst, const IR::Value& value) {
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Alias(inst, value);
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Alias(inst, value);
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}
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}
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@ -22,7 +22,8 @@ class EmitContext;
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void EmitPhi(EmitContext& ctx, IR::Inst& inst);
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void EmitPhi(EmitContext& ctx, IR::Inst& inst);
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void EmitVoid(EmitContext& ctx);
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void EmitVoid(EmitContext& ctx);
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void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitDummyReference(EmitContext&);
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void EmitConditionRef(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitReference(EmitContext&);
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value);
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value);
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void EmitJoin(EmitContext& ctx);
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void EmitJoin(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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@ -21,7 +21,7 @@ void EmitPhi(EmitContext&, IR::Inst&) {}
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void EmitVoid(EmitContext&) {}
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void EmitVoid(EmitContext&) {}
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void EmitDummyReference(EmitContext&) {}
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void EmitReference(EmitContext&) {}
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value) {
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value) {
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if (phi == value) {
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if (phi == value) {
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@ -139,6 +139,7 @@ void RegAlloc::Free(Id id) {
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/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
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/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::Identity:
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case IR::Opcode::Identity:
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case IR::Opcode::ConditionRef:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastU32F32:
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case IR::Opcode::BitCastU32F32:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastU64F64:
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@ -469,7 +469,15 @@ Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
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return id;
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return id;
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}
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}
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void EmitDummyReference(EmitContext&) {}
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Id EmitConditionRef(EmitContext& ctx, const IR::Value& value) {
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const Id id{ctx.Def(value)};
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if (!Sirit::ValidId(id)) {
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throw NotImplementedException("Forward identity declaration");
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}
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return id;
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}
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void EmitReference(EmitContext&) {}
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void EmitPhiMove(EmitContext&) {
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void EmitPhiMove(EmitContext&) {
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throw LogicError("Unreachable instruction");
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throw LogicError("Unreachable instruction");
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@ -23,7 +23,8 @@ class EmitContext;
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
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void EmitVoid(EmitContext& ctx);
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void EmitVoid(EmitContext& ctx);
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
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void EmitDummyReference(EmitContext&);
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Id EmitConditionRef(EmitContext& ctx, const IR::Value& value);
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void EmitReference(EmitContext&);
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void EmitPhiMove(EmitContext&);
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void EmitPhiMove(EmitContext&);
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void EmitJoin(EmitContext& ctx);
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void EmitJoin(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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@ -61,8 +61,12 @@ F64 IREmitter::Imm64(f64 value) const {
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return F64{Value{value}};
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return F64{Value{value}};
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}
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}
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void IREmitter::DummyReference(const Value& value) {
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U1 IREmitter::ConditionRef(const U1& value) {
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Inst(Opcode::DummyReference, value);
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return Inst<U1>(Opcode::ConditionRef, value);
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}
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void IREmitter::Reference(const Value& value) {
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Inst(Opcode::Reference, value);
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}
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}
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void IREmitter::PhiMove(IR::Inst& phi, const Value& value) {
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void IREmitter::PhiMove(IR::Inst& phi, const Value& value) {
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@ -32,7 +32,9 @@ public:
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[[nodiscard]] U64 Imm64(s64 value) const;
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[[nodiscard]] U64 Imm64(s64 value) const;
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[[nodiscard]] F64 Imm64(f64 value) const;
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[[nodiscard]] F64 Imm64(f64 value) const;
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void DummyReference(const Value& value);
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U1 ConditionRef(const U1& value);
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void Reference(const Value& value);
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void PhiMove(IR::Inst& phi, const Value& value);
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void PhiMove(IR::Inst& phi, const Value& value);
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void Prologue();
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void Prologue();
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@ -56,7 +56,8 @@ Inst::~Inst() {
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bool Inst::MayHaveSideEffects() const noexcept {
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bool Inst::MayHaveSideEffects() const noexcept {
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switch (op) {
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switch (op) {
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case Opcode::DummyReference:
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case Opcode::ConditionRef:
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case Opcode::Reference:
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case Opcode::PhiMove:
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case Opcode::PhiMove:
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case Opcode::Prologue:
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::Epilogue:
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@ -6,7 +6,8 @@
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OPCODE(Phi, Opaque, )
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OPCODE(Phi, Opaque, )
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OPCODE(Identity, Opaque, Opaque, )
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OPCODE(Identity, Opaque, Opaque, )
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OPCODE(Void, Void, )
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OPCODE(Void, Void, )
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OPCODE(DummyReference, Void, Opaque, )
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OPCODE(ConditionRef, U1, U1, )
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OPCODE(Reference, Void, Opaque, )
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OPCODE(PhiMove, Void, Opaque, Opaque, )
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OPCODE(PhiMove, Void, Opaque, Opaque, )
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// Special operations
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// Special operations
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@ -703,8 +703,7 @@ private:
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// Implement if header block
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// Implement if header block
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IR::IREmitter ir{*current_block};
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IR::IREmitter ir{*current_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
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ir.DummyReference(cond);
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const size_t if_node_index{syntax_list.size()};
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const size_t if_node_index{syntax_list.size()};
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syntax_list.emplace_back();
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syntax_list.emplace_back();
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@ -754,8 +753,7 @@ private:
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// The continue block is located at the end of the loop
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// The continue block is located at the end of the loop
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IR::IREmitter ir{*continue_block};
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IR::IREmitter ir{*continue_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
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ir.DummyReference(cond);
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IR::Block* const body_block{syntax_list.at(body_block_index).data.block};
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IR::Block* const body_block{syntax_list.at(body_block_index).data.block};
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loop_header_block->AddBranch(body_block);
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loop_header_block->AddBranch(body_block);
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@ -791,8 +789,7 @@ private:
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IR::Block* const skip_block{MergeBlock(parent, stmt)};
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IR::Block* const skip_block{MergeBlock(parent, stmt)};
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IR::IREmitter ir{*current_block};
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IR::IREmitter ir{*current_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
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ir.DummyReference(cond);
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current_block->AddBranch(break_block);
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current_block->AddBranch(break_block);
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current_block->AddBranch(skip_block);
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current_block->AddBranch(skip_block);
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current_block = skip_block;
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current_block = skip_block;
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