Merge pull request #6900 from ameerj/attr-reorder
structured_control_flow: Add DemoteCombinationPass
This commit is contained in:
commit
b2572a56d3
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@ -20,6 +20,7 @@
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#include "shader_recompiler/frontend/maxwell/decode.h"
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#include "shader_recompiler/frontend/maxwell/structured_control_flow.h"
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#include "shader_recompiler/frontend/maxwell/translate/translate.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/object_pool.h"
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namespace Shader::Maxwell {
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@ -652,7 +653,7 @@ class TranslatePass {
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public:
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TranslatePass(ObjectPool<IR::Inst>& inst_pool_, ObjectPool<IR::Block>& block_pool_,
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ObjectPool<Statement>& stmt_pool_, Environment& env_, Statement& root_stmt,
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IR::AbstractSyntaxList& syntax_list_)
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IR::AbstractSyntaxList& syntax_list_, const HostTranslateInfo& host_info)
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: stmt_pool{stmt_pool_}, inst_pool{inst_pool_}, block_pool{block_pool_}, env{env_},
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syntax_list{syntax_list_} {
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Visit(root_stmt, nullptr, nullptr);
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@ -660,6 +661,9 @@ public:
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IR::Block& first_block{*syntax_list.front().data.block};
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IR::IREmitter ir(first_block, first_block.begin());
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ir.Prologue();
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if (uses_demote_to_helper && host_info.needs_demote_reorder) {
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DemoteCombinationPass();
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}
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}
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private:
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@ -809,7 +813,14 @@ private:
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}
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case StatementType::Return: {
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ensure_block();
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IR::IREmitter{*current_block}.Epilogue();
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IR::Block* return_block{block_pool.Create(inst_pool)};
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IR::IREmitter{*return_block}.Epilogue();
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current_block->AddBranch(return_block);
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auto& merge{syntax_list.emplace_back()};
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merge.type = IR::AbstractSyntaxNode::Type::Block;
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merge.data.block = return_block;
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current_block = nullptr;
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syntax_list.emplace_back().type = IR::AbstractSyntaxNode::Type::Return;
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break;
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@ -824,6 +835,7 @@ private:
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auto& merge{syntax_list.emplace_back()};
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merge.type = IR::AbstractSyntaxNode::Type::Block;
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merge.data.block = demote_block;
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uses_demote_to_helper = true;
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break;
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}
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case StatementType::Unreachable: {
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@ -855,11 +867,117 @@ private:
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return block_pool.Create(inst_pool);
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}
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void DemoteCombinationPass() {
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using Type = IR::AbstractSyntaxNode::Type;
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std::vector<IR::Block*> demote_blocks;
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std::vector<IR::U1> demote_conds;
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u32 num_epilogues{};
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u32 branch_depth{};
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for (const IR::AbstractSyntaxNode& node : syntax_list) {
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if (node.type == Type::If) {
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++branch_depth;
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}
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if (node.type == Type::EndIf) {
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--branch_depth;
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}
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if (node.type != Type::Block) {
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continue;
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}
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if (branch_depth > 1) {
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// Skip reordering nested demote branches.
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continue;
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}
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for (const IR::Inst& inst : node.data.block->Instructions()) {
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const IR::Opcode op{inst.GetOpcode()};
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if (op == IR::Opcode::DemoteToHelperInvocation) {
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demote_blocks.push_back(node.data.block);
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break;
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}
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if (op == IR::Opcode::Epilogue) {
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++num_epilogues;
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}
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}
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}
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if (demote_blocks.size() == 0) {
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return;
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}
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if (num_epilogues > 1) {
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LOG_DEBUG(Shader, "Combining demotes with more than one return is not implemented.");
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return;
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}
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s64 last_iterator_offset{};
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auto& asl{syntax_list};
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for (const IR::Block* demote_block : demote_blocks) {
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const auto start_it{asl.begin() + last_iterator_offset};
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auto asl_it{std::find_if(start_it, asl.end(), [&](const IR::AbstractSyntaxNode& asn) {
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return asn.type == Type::If && asn.data.if_node.body == demote_block;
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})};
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if (asl_it == asl.end()) {
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// Demote without a conditional branch.
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// No need to proceed since all fragment instances will be demoted regardless.
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return;
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}
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const IR::Block* const end_if = asl_it->data.if_node.merge;
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demote_conds.push_back(asl_it->data.if_node.cond);
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last_iterator_offset = std::distance(asl.begin(), asl_it);
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asl_it = asl.erase(asl_it);
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asl_it = std::find_if(asl_it, asl.end(), [&](const IR::AbstractSyntaxNode& asn) {
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return asn.type == Type::Block && asn.data.block == demote_block;
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});
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asl_it = asl.erase(asl_it);
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asl_it = std::find_if(asl_it, asl.end(), [&](const IR::AbstractSyntaxNode& asn) {
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return asn.type == Type::EndIf && asn.data.end_if.merge == end_if;
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});
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asl_it = asl.erase(asl_it);
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}
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const auto epilogue_func{[](const IR::AbstractSyntaxNode& asn) {
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if (asn.type != Type::Block) {
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return false;
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}
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for (const auto& inst : asn.data.block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::Epilogue) {
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return true;
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}
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}
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return false;
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}};
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const auto reverse_it{std::find_if(asl.rbegin(), asl.rend(), epilogue_func)};
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const auto return_block_it{(reverse_it + 1).base()};
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IR::IREmitter ir{*(return_block_it - 1)->data.block};
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IR::U1 cond(IR::Value(false));
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for (const auto& demote_cond : demote_conds) {
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cond = ir.LogicalOr(cond, demote_cond);
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}
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cond.Inst()->DestructiveAddUsage(1);
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IR::AbstractSyntaxNode demote_if_node{};
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demote_if_node.type = Type::If;
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demote_if_node.data.if_node.cond = cond;
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demote_if_node.data.if_node.body = demote_blocks[0];
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demote_if_node.data.if_node.merge = return_block_it->data.block;
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IR::AbstractSyntaxNode demote_node{};
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demote_node.type = Type::Block;
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demote_node.data.block = demote_blocks[0];
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IR::AbstractSyntaxNode demote_endif_node{};
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demote_endif_node.type = Type::EndIf;
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demote_endif_node.data.end_if.merge = return_block_it->data.block;
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asl.insert(return_block_it, demote_endif_node);
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asl.insert(return_block_it, demote_node);
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asl.insert(return_block_it, demote_if_node);
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}
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ObjectPool<Statement>& stmt_pool;
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ObjectPool<IR::Inst>& inst_pool;
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ObjectPool<IR::Block>& block_pool;
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Environment& env;
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IR::AbstractSyntaxList& syntax_list;
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bool uses_demote_to_helper{};
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// TODO: C++20 Remove this when all compilers support constexpr std::vector
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#if __cpp_lib_constexpr_vector >= 201907
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@ -871,12 +989,13 @@ private:
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} // Anonymous namespace
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IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Environment& env, Flow::CFG& cfg) {
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Environment& env, Flow::CFG& cfg,
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const HostTranslateInfo& host_info) {
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ObjectPool<Statement> stmt_pool{64};
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GotoPass goto_pass{cfg, stmt_pool};
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Statement& root{goto_pass.RootStatement()};
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IR::AbstractSyntaxList syntax_list;
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TranslatePass{inst_pool, block_pool, stmt_pool, env, root, syntax_list};
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TranslatePass{inst_pool, block_pool, stmt_pool, env, root, syntax_list, host_info};
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return syntax_list;
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}
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@ -11,10 +11,13 @@
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#include "shader_recompiler/frontend/maxwell/control_flow.h"
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#include "shader_recompiler/object_pool.h"
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namespace Shader::Maxwell {
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namespace Shader {
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struct HostTranslateInfo;
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namespace Maxwell {
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[[nodiscard]] IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool, Environment& env,
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Flow::CFG& cfg);
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Flow::CFG& cfg, const HostTranslateInfo& host_info);
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} // namespace Shader::Maxwell
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} // namespace Maxwell
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} // namespace Shader
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@ -130,7 +130,7 @@ void AddNVNStorageBuffers(IR::Program& program) {
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IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Environment& env, Flow::CFG& cfg, const HostTranslateInfo& host_info) {
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IR::Program program;
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program.syntax_list = BuildASL(inst_pool, block_pool, env, cfg);
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program.syntax_list = BuildASL(inst_pool, block_pool, env, cfg, host_info);
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program.blocks = GenerateBlocks(program.syntax_list);
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program.post_order_blocks = PostOrder(program.syntax_list.front());
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program.stage = env.ShaderStage();
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@ -13,6 +13,7 @@ namespace Shader {
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struct HostTranslateInfo {
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bool support_float16{}; ///< True when the device supports 16-bit floats
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bool support_int64{}; ///< True when the device supports 64-bit integers
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bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
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};
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} // namespace Shader
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@ -156,6 +156,10 @@ public:
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return shader_backend;
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}
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bool IsAmd() const {
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return vendor_name == "ATI Technologies Inc.";
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}
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private:
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static bool TestVariableAoffi();
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static bool TestPreciseBug();
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@ -219,6 +219,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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host_info{
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.support_float16 = false,
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.support_int64 = device.HasShaderInt64(),
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.needs_demote_reorder = device.IsAmd(),
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} {
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if (use_asynchronous_shaders) {
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workers = CreateWorkers();
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@ -325,6 +325,8 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::Engines::Maxw
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host_info = Shader::HostTranslateInfo{
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.support_float16 = device.IsFloat16Supported(),
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.support_int64 = device.IsShaderInt64Supported(),
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.needs_demote_reorder = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY_KHR ||
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driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE_KHR,
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};
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}
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