texture_cache: Implement guest flushing
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de0b1cb2b2
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@ -722,7 +722,7 @@ void RasterizerOpenGL::FlushRegion(CacheAddr addr, u64 size) {
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if (!addr || !size) {
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if (!addr || !size) {
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return;
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return;
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}
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}
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// texture_cache.FlushRegion(addr, size);
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texture_cache.FlushRegion(addr, size);
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global_cache.FlushRegion(addr, size);
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global_cache.FlushRegion(addr, size);
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}
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}
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@ -738,7 +738,9 @@ void RasterizerOpenGL::InvalidateRegion(CacheAddr addr, u64 size) {
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}
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}
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void RasterizerOpenGL::FlushAndInvalidateRegion(CacheAddr addr, u64 size) {
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void RasterizerOpenGL::FlushAndInvalidateRegion(CacheAddr addr, u64 size) {
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FlushRegion(addr, size);
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if (Settings::values.use_accurate_gpu_emulation) {
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FlushRegion(addr, size);
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}
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InvalidateRegion(addr, size);
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InvalidateRegion(addr, size);
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}
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}
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@ -63,6 +63,9 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
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std::vector<u8>& staging_buffer) {
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std::vector<u8>& staging_buffer) {
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MICROPROFILE_SCOPE(GPU_Load_Texture);
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MICROPROFILE_SCOPE(GPU_Load_Texture);
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const auto host_ptr{memory_manager.GetPointer(gpu_addr)};
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const auto host_ptr{memory_manager.GetPointer(gpu_addr)};
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if (!host_ptr) {
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return;
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}
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if (params.is_tiled) {
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if (params.is_tiled) {
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture target {}",
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture target {}",
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params.block_width, static_cast<u32>(params.target));
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params.block_width, static_cast<u32>(params.target));
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@ -103,7 +106,10 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
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void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
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void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
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std::vector<u8>& staging_buffer) {
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std::vector<u8>& staging_buffer) {
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MICROPROFILE_SCOPE(GPU_Flush_Texture);
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MICROPROFILE_SCOPE(GPU_Flush_Texture);
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auto host_ptr = memory_manager.GetPointer(gpu_addr);
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const auto host_ptr{memory_manager.GetPointer(gpu_addr)};
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if (!host_ptr) {
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return;
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}
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if (params.is_tiled) {
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if (params.is_tiled) {
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {}", params.block_width);
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {}", params.block_width);
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for (u32 level = 0; level < params.num_levels; ++level) {
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for (u32 level = 0; level < params.num_levels; ++level) {
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@ -112,25 +118,22 @@ void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
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staging_buffer.data() + host_offset, level);
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staging_buffer.data() + host_offset, level);
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}
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}
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} else {
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} else {
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UNIMPLEMENTED();
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/*
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ASSERT(params.target == SurfaceTarget::Texture2D);
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ASSERT(params.target == SurfaceTarget::Texture2D);
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ASSERT(params.num_levels == 1);
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ASSERT(params.num_levels == 1);
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const u32 bpp{params.GetFormatBpp() / 8};
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const u32 bpp{params.GetBytesPerPixel()};
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const u32 copy_size{params.width * bpp};
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const u32 copy_size{params.width * bpp};
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if (params.pitch == copy_size) {
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if (params.pitch == copy_size) {
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std::memcpy(host_ptr, staging_buffer.data(), memory_size);
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std::memcpy(host_ptr, staging_buffer.data(), guest_memory_size);
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} else {
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} else {
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u8* start{host_ptr};
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u8* start{host_ptr};
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const u8* read_to{staging_buffer.data()};
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const u8* read_to{staging_buffer.data()};
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for (u32 h = params.GetHeight(); h > 0; --h) {
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for (u32 h = params.height; h > 0; --h) {
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std::memcpy(start, read_to, copy_size);
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std::memcpy(start, read_to, copy_size);
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start += params.GetPitch();
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start += params.pitch;
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read_to += copy_size;
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read_to += copy_size;
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}
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}
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}
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}
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*/
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}
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}
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}
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}
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@ -61,6 +61,20 @@ public:
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}
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}
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}
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}
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void FlushRegion(CacheAddr addr, std::size_t size) {
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auto surfaces = GetSurfacesInRegion(addr, size);
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if (surfaces.empty()) {
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return;
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}
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std::sort(surfaces.begin(), surfaces.end(),
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[](const TSurface& a, const TSurface& b) -> bool {
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return a->GetModificationTick() < b->GetModificationTick();
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});
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for (const auto& surface : surfaces) {
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FlushSurface(surface);
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}
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}
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TView GetTextureSurface(const Tegra::Texture::FullTextureInfo& config,
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TView GetTextureSurface(const Tegra::Texture::FullTextureInfo& config,
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const VideoCommon::Shader::Sampler& entry) {
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const VideoCommon::Shader::Sampler& entry) {
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const auto gpu_addr{config.tic.Address()};
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const auto gpu_addr{config.tic.Address()};
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